From 08f2dc115ead63161f56b7ada4a2092b61ce6083 Mon Sep 17 00:00:00 2001 From: michael-roe <2479665+michael-roe@users.noreply.github.com> Date: Wed, 1 Jun 2022 14:58:29 +0100 Subject: [PATCH] Added some MIPS features. (#241) Co-authored-by: Michael Roe --- include/cpuinfo_mips.h | 24 +++++++++++++++----- include/internal/hwcaps.h | 7 ++++++ src/impl_mips_linux_or_android.c | 13 +++++++---- test/cpuinfo_mips_test.cc | 38 ++++++++++++++++++++++++++++++++ 4 files changed, 73 insertions(+), 9 deletions(-) diff --git a/include/cpuinfo_mips.h b/include/cpuinfo_mips.h index 9e5e7fc..321d3c8 100644 --- a/include/cpuinfo_mips.h +++ b/include/cpuinfo_mips.h @@ -21,11 +21,20 @@ CPU_FEATURES_START_CPP_NAMESPACE typedef struct { - int msa : 1; // MIPS SIMD Architecture - // https://www.mips.com/products/architectures/ase/simd/ - int eva : 1; // Enhanced Virtual Addressing - // https://www.mips.com/products/architectures/mips64/ - int r6 : 1; // True if is release 6 of the processor. + int msa : 1; // MIPS SIMD Architecture + // https://www.mips.com/products/architectures/ase/simd/ + int eva : 1; // Enhanced Virtual Addressing + // https://www.mips.com/products/architectures/mips64/ + int r6 : 1; // True if is release 6 of the processor. + int mips16 : 1; // Compressed instructions + int mdmx : 1; // MIPS Digital Media Extension + int mips3d : 1; // 3D graphics acceleration + // MIPS(r) Architecture for Programmers, Volume IV-c + int smart : 1; // Smart-card cryptography + // MIPS(r) Architecture for Programmers, Volume IV-d + int dsp : 1; // Digital Signal Processing + // MIPS(r) Architecture for Programmers, Volume IV-e + // https://www.mips.com/products/architectures/ase/dsp/ // Make sure to update MipsFeaturesEnum below if you add a field here. } MipsFeatures; @@ -43,6 +52,11 @@ typedef enum { MIPS_MSA, MIPS_EVA, MIPS_R6, + MIPS_MIPS16, + MIPS_MDMX, + MIPS_MIPS3D, + MIPS_SMART, + MIPS_DSP, MIPS_LAST_, } MipsFeaturesEnum; diff --git a/include/internal/hwcaps.h b/include/internal/hwcaps.h index cc2c984..3f45aed 100644 --- a/include/internal/hwcaps.h +++ b/include/internal/hwcaps.h @@ -117,6 +117,13 @@ CPU_FEATURES_START_CPP_NAMESPACE #define MIPS_HWCAP_R6 (1UL << 0) #define MIPS_HWCAP_MSA (1UL << 1) #define MIPS_HWCAP_CRC32 (1UL << 2) +#define MIPS_HWCAP_MIPS16 (1UL << 3) +#define MIPS_HWCAP_MDMX (1UL << 4) +#define MIPS_HWCAP_MIPS3D (1UL << 5) +#define MIPS_HWCAP_SMARTMIPS (1UL << 6) +#define MIPS_HWCAP_DSP (1UL << 7) +#define MIPS_HWCAP_DSP2 (1UL << 8) +#define MIPS_HWCAP_DSP3 (1UL << 9) // http://elixir.free-electrons.com/linux/latest/source/arch/powerpc/include/uapi/asm/cputable.h #ifndef _UAPI__ASM_POWERPC_CPUTABLE_H diff --git a/src/impl_mips_linux_or_android.c b/src/impl_mips_linux_or_android.c index 9a3dc2f..2322ecf 100644 --- a/src/impl_mips_linux_or_android.c +++ b/src/impl_mips_linux_or_android.c @@ -20,10 +20,15 @@ //////////////////////////////////////////////////////////////////////////////// // Definitions for introspection. //////////////////////////////////////////////////////////////////////////////// -#define INTROSPECTION_TABLE \ - LINE(MIPS_MSA, msa, "msa", MIPS_HWCAP_MSA, 0) \ - LINE(MIPS_EVA, eva, "eva", 0, 0) \ - LINE(MIPS_R6, r6, "r6", MIPS_HWCAP_R6, 0) +#define INTROSPECTION_TABLE \ + LINE(MIPS_MSA, msa, "msa", MIPS_HWCAP_MSA, 0) \ + LINE(MIPS_EVA, eva, "eva", 0, 0) \ + LINE(MIPS_R6, r6, "r6", MIPS_HWCAP_R6, 0) \ + LINE(MIPS_MIPS16, mips16, "mips16", MIPS_HWCAP_MIPS16, 0) \ + LINE(MIPS_MDMX, mdmx, "mdmx", MIPS_HWCAP_MDMX, 0) \ + LINE(MIPS_MIPS3D, mips3d, "mips3d", MIPS_HWCAP_MIPS3D, 0) \ + LINE(MIPS_SMART, smart, "smartmips", MIPS_HWCAP_SMARTMIPS, 0) \ + LINE(MIPS_DSP, dsp, "dsp", MIPS_HWCAP_DSP, 0) #define INTROSPECTION_PREFIX Mips #define INTROSPECTION_ENUM_PREFIX MIPS #include "define_introspection_and_hwcaps.inl" diff --git a/test/cpuinfo_mips_test.cc b/test/cpuinfo_mips_test.cc index a01624a..edcb381 100644 --- a/test/cpuinfo_mips_test.cc +++ b/test/cpuinfo_mips_test.cc @@ -69,6 +69,12 @@ VPE : 0 const auto info = GetMipsInfo(); EXPECT_FALSE(info.features.msa); EXPECT_TRUE(info.features.eva); + EXPECT_FALSE(info.features.r6); + EXPECT_TRUE(info.features.mips16); + EXPECT_FALSE(info.features.mdmx); + EXPECT_FALSE(info.features.mips3d); + EXPECT_FALSE(info.features.smart); + EXPECT_TRUE(info.features.dsp); } TEST(CpuinfoMipsTest, AR7161) { @@ -95,6 +101,7 @@ VCEI exceptions : not available const auto info = GetMipsInfo(); EXPECT_FALSE(info.features.msa); EXPECT_FALSE(info.features.eva); + EXPECT_TRUE(info.features.mips16); } TEST(CpuinfoMipsTest, Goldfish) { @@ -122,5 +129,36 @@ VCEI exceptions : not available EXPECT_FALSE(info.features.eva); } +TEST(CpuinfoMipsTest, BCM1250) { + ResetHwcaps(); + auto& fs = GetEmptyFilesystem(); + fs.CreateFile("/proc/cpuinfo", R"(system type : SiByte BCM91250A (SWARM) +processor : 0 +cpu model : SiByte SB1 V0.2 FPU V0.2 +BogoMIPS : 532.48 +wait instruction : no +microsecond timers : yes +tlb_entries : 64 +extra interrupt vector : yes +hardware watchpoint : yes, count: 1, address/irw mask: [0x0ff8] +isa : mips1 mips2 mips3 mips4 mips5 mips32r1 mips32r2 mips64r1 mips64r2 +ASEs implemented : mdmx mips3d +shadow register sets : 1 +kscratch registers : 0 +package : 0 +core : 0 +VCED exceptions : not available +VCEI exceptions : not available +)"); + const auto info = GetMipsInfo(); + EXPECT_FALSE(info.features.msa); + EXPECT_FALSE(info.features.eva); + EXPECT_FALSE(info.features.mips16); + EXPECT_TRUE(info.features.mdmx); + EXPECT_TRUE(info.features.mips3d); + EXPECT_FALSE(info.features.smart); + EXPECT_FALSE(info.features.dsp); +} + } // namespace } // namespace cpu_features