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Add Intel Raptor Lake uarch detection (#283)

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Mykola Hohsadze 2022-11-08 14:35:50 +00:00 committed by GitHub
parent b7bc447203
commit 19799486d2
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3 changed files with 72 additions and 53 deletions

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@ -161,6 +161,7 @@ typedef enum {
INTEL_SPR, // SAPPHIRE RAPIDS INTEL_SPR, // SAPPHIRE RAPIDS
INTEL_ADL, // ALDER LAKE INTEL_ADL, // ALDER LAKE
INTEL_RCL, // ROCKET LAKE INTEL_RCL, // ROCKET LAKE
INTEL_RPL, // RAPTOR LAKE
INTEL_KNIGHTS_M, // KNIGHTS MILL INTEL_KNIGHTS_M, // KNIGHTS MILL
INTEL_KNIGHTS_L, // KNIGHTS LANDING INTEL_KNIGHTS_L, // KNIGHTS LANDING
INTEL_KNIGHTS_F, // KNIGHTS FERRY INTEL_KNIGHTS_F, // KNIGHTS FERRY

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@ -581,6 +581,9 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) {
case CPUID(0x06, 0xA7): case CPUID(0x06, 0xA7):
// https://en.wikichip.org/wiki/intel/microarchitectures/rocket_lake // https://en.wikichip.org/wiki/intel/microarchitectures/rocket_lake
return INTEL_RCL; return INTEL_RCL;
case CPUID(0x06, 0xB7):
// https://en.wikichip.org/wiki/intel/microarchitectures/raptor_lake
return INTEL_RPL;
case CPUID(0x06, 0x85): case CPUID(0x06, 0x85):
// https://en.wikichip.org/wiki/intel/microarchitectures/knights_mill // https://en.wikichip.org/wiki/intel/microarchitectures/knights_mill
return INTEL_KNIGHTS_M; return INTEL_KNIGHTS_M;
@ -1948,6 +1951,7 @@ CacheInfo GetX86CacheInfo(void) {
LINE(INTEL_SPR) \ LINE(INTEL_SPR) \
LINE(INTEL_ADL) \ LINE(INTEL_ADL) \
LINE(INTEL_RCL) \ LINE(INTEL_RCL) \
LINE(INTEL_RPL) \
LINE(INTEL_KNIGHTS_M) \ LINE(INTEL_KNIGHTS_M) \
LINE(INTEL_KNIGHTS_L) \ LINE(INTEL_KNIGHTS_L) \
LINE(INTEL_KNIGHTS_F) \ LINE(INTEL_KNIGHTS_F) \

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@ -1610,6 +1610,20 @@ TEST_F(CpuidX86Test, INTEL_ATOM_TMT_JASPER_LAKE) {
EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_ATOM_TMT); EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_ATOM_TMT);
} }
// http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00B0671_RaptorLake_02_CPUID.txt
TEST_F(CpuidX86Test, INTEL_RAPTOR_LAKE) {
cpu().SetLeaves({
{{0x00000000, 0}, Leaf{0x00000020, 0x756E6547, 0x6C65746E, 0x49656E69}},
{{0x00000001, 0}, Leaf{0x000B0671, 0x00800800, 0x7FFAFBBF, 0xBFEBFBFF}},
});
const auto info = GetX86Info();
EXPECT_STREQ(info.vendor, CPU_FEATURES_VENDOR_GENUINE_INTEL);
EXPECT_EQ(info.family, 0x06);
EXPECT_EQ(info.model, 0xB7);
EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_RPL);
}
// http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00306F2_HaswellEP2_CPUID.txt // http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00306F2_HaswellEP2_CPUID.txt
TEST_F(CpuidX86Test, INTEL_HASWELL_LZCNT) { TEST_F(CpuidX86Test, INTEL_HASWELL_LZCNT) {
cpu().SetLeaves({ cpu().SetLeaves({