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Add Intel Raptor Lake uarch detection (#283)

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Mykola Hohsadze 2022-11-08 14:35:50 +00:00 committed by GitHub
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commit 19799486d2
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3 changed files with 72 additions and 53 deletions
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107
include/cpuinfo_x86.h
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@ -129,59 +129,60 @@ CacheInfo GetX86CacheInfo(void);
typedef enum { typedef enum {
X86_UNKNOWN, X86_UNKNOWN,
ZHAOXIN_ZHANGJIANG, // ZhangJiang ZHAOXIN_ZHANGJIANG, // ZhangJiang
ZHAOXIN_WUDAOKOU, // WuDaoKou ZHAOXIN_WUDAOKOU, // WuDaoKou
ZHAOXIN_LUJIAZUI, // LuJiaZui ZHAOXIN_LUJIAZUI, // LuJiaZui
ZHAOXIN_YONGFENG, // YongFeng ZHAOXIN_YONGFENG, // YongFeng
INTEL_80486, // 80486 INTEL_80486, // 80486
INTEL_P5, // P5 INTEL_P5, // P5
INTEL_LAKEMONT, // LAKEMONT INTEL_LAKEMONT, // LAKEMONT
INTEL_CORE, // CORE INTEL_CORE, // CORE
INTEL_PNR, // PENRYN INTEL_PNR, // PENRYN
INTEL_NHM, // NEHALEM INTEL_NHM, // NEHALEM
INTEL_ATOM_BNL, // BONNELL INTEL_ATOM_BNL, // BONNELL
INTEL_WSM, // WESTMERE INTEL_WSM, // WESTMERE
INTEL_SNB, // SANDYBRIDGE INTEL_SNB, // SANDYBRIDGE
INTEL_IVB, // IVYBRIDGE INTEL_IVB, // IVYBRIDGE
INTEL_ATOM_SMT, // SILVERMONT INTEL_ATOM_SMT, // SILVERMONT
INTEL_HSW, // HASWELL INTEL_HSW, // HASWELL
INTEL_BDW, // BROADWELL INTEL_BDW, // BROADWELL
INTEL_SKL, // SKYLAKE INTEL_SKL, // SKYLAKE
INTEL_CCL, // CASCADELAKE INTEL_CCL, // CASCADELAKE
INTEL_ATOM_GMT, // GOLDMONT INTEL_ATOM_GMT, // GOLDMONT
INTEL_ATOM_GMT_PLUS, // GOLDMONT+ INTEL_ATOM_GMT_PLUS, // GOLDMONT+
INTEL_ATOM_TMT, // TREMONT INTEL_ATOM_TMT, // TREMONT
INTEL_KBL, // KABY LAKE INTEL_KBL, // KABY LAKE
INTEL_CFL, // COFFEE LAKE INTEL_CFL, // COFFEE LAKE
INTEL_WHL, // WHISKEY LAKE INTEL_WHL, // WHISKEY LAKE
INTEL_CML, // COMET LAKE INTEL_CML, // COMET LAKE
INTEL_CNL, // CANNON LAKE INTEL_CNL, // CANNON LAKE
INTEL_ICL, // ICE LAKE INTEL_ICL, // ICE LAKE
INTEL_TGL, // TIGER LAKE INTEL_TGL, // TIGER LAKE
INTEL_SPR, // SAPPHIRE RAPIDS INTEL_SPR, // SAPPHIRE RAPIDS
INTEL_ADL, // ALDER LAKE INTEL_ADL, // ALDER LAKE
INTEL_RCL, // ROCKET LAKE INTEL_RCL, // ROCKET LAKE
INTEL_KNIGHTS_M, // KNIGHTS MILL INTEL_RPL, // RAPTOR LAKE
INTEL_KNIGHTS_L, // KNIGHTS LANDING INTEL_KNIGHTS_M, // KNIGHTS MILL
INTEL_KNIGHTS_F, // KNIGHTS FERRY INTEL_KNIGHTS_L, // KNIGHTS LANDING
INTEL_KNIGHTS_C, // KNIGHTS CORNER INTEL_KNIGHTS_F, // KNIGHTS FERRY
INTEL_NETBURST, // NETBURST INTEL_KNIGHTS_C, // KNIGHTS CORNER
AMD_HAMMER, // K8 HAMMER INTEL_NETBURST, // NETBURST
AMD_K10, // K10 AMD_HAMMER, // K8 HAMMER
AMD_K11, // K11 AMD_K10, // K10
AMD_K12, // K12 LLANO AMD_K11, // K11
AMD_BOBCAT, // K14 BOBCAT AMD_K12, // K12 LLANO
AMD_PILEDRIVER, // K15 PILEDRIVER AMD_BOBCAT, // K14 BOBCAT
AMD_STREAMROLLER, // K15 STREAMROLLER AMD_PILEDRIVER, // K15 PILEDRIVER
AMD_EXCAVATOR, // K15 EXCAVATOR AMD_STREAMROLLER, // K15 STREAMROLLER
AMD_BULLDOZER, // K15 BULLDOZER AMD_EXCAVATOR, // K15 EXCAVATOR
AMD_JAGUAR, // K16 JAGUAR AMD_BULLDOZER, // K15 BULLDOZER
AMD_PUMA, // K16 PUMA AMD_JAGUAR, // K16 JAGUAR
AMD_ZEN, // K17 ZEN AMD_PUMA, // K16 PUMA
AMD_ZEN_PLUS, // K17 ZEN+ AMD_ZEN, // K17 ZEN
AMD_ZEN2, // K17 ZEN 2 AMD_ZEN_PLUS, // K17 ZEN+
AMD_ZEN3, // K19 ZEN 3 AMD_ZEN2, // K17 ZEN 2
AMD_ZEN4, // K19 ZEN 4 AMD_ZEN3, // K19 ZEN 3
AMD_ZEN4, // K19 ZEN 4
X86_MICROARCHITECTURE_LAST_, X86_MICROARCHITECTURE_LAST_,
} X86Microarchitecture; } X86Microarchitecture;

4
src/impl_x86__base_implementation.inl
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@ -581,6 +581,9 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) {
case CPUID(0x06, 0xA7): case CPUID(0x06, 0xA7):
// https://en.wikichip.org/wiki/intel/microarchitectures/rocket_lake // https://en.wikichip.org/wiki/intel/microarchitectures/rocket_lake
return INTEL_RCL; return INTEL_RCL;
case CPUID(0x06, 0xB7):
// https://en.wikichip.org/wiki/intel/microarchitectures/raptor_lake
return INTEL_RPL;
case CPUID(0x06, 0x85): case CPUID(0x06, 0x85):
// https://en.wikichip.org/wiki/intel/microarchitectures/knights_mill // https://en.wikichip.org/wiki/intel/microarchitectures/knights_mill
return INTEL_KNIGHTS_M; return INTEL_KNIGHTS_M;
@ -1948,6 +1951,7 @@ CacheInfo GetX86CacheInfo(void) {
LINE(INTEL_SPR) \ LINE(INTEL_SPR) \
LINE(INTEL_ADL) \ LINE(INTEL_ADL) \
LINE(INTEL_RCL) \ LINE(INTEL_RCL) \
LINE(INTEL_RPL) \
LINE(INTEL_KNIGHTS_M) \ LINE(INTEL_KNIGHTS_M) \
LINE(INTEL_KNIGHTS_L) \ LINE(INTEL_KNIGHTS_L) \
LINE(INTEL_KNIGHTS_F) \ LINE(INTEL_KNIGHTS_F) \

14
test/cpuinfo_x86_test.cc
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@ -1610,6 +1610,20 @@ TEST_F(CpuidX86Test, INTEL_ATOM_TMT_JASPER_LAKE) {
EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_ATOM_TMT); EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_ATOM_TMT);
} }
// http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00B0671_RaptorLake_02_CPUID.txt
TEST_F(CpuidX86Test, INTEL_RAPTOR_LAKE) {
cpu().SetLeaves({
{{0x00000000, 0}, Leaf{0x00000020, 0x756E6547, 0x6C65746E, 0x49656E69}},
{{0x00000001, 0}, Leaf{0x000B0671, 0x00800800, 0x7FFAFBBF, 0xBFEBFBFF}},
});
const auto info = GetX86Info();
EXPECT_STREQ(info.vendor, CPU_FEATURES_VENDOR_GENUINE_INTEL);
EXPECT_EQ(info.family, 0x06);
EXPECT_EQ(info.model, 0xB7);
EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_RPL);
}
// http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00306F2_HaswellEP2_CPUID.txt // http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00306F2_HaswellEP2_CPUID.txt
TEST_F(CpuidX86Test, INTEL_HASWELL_LZCNT) { TEST_F(CpuidX86Test, INTEL_HASWELL_LZCNT) {
cpu().SetLeaves({ cpu().SetLeaves({