From 1d02169588ceb7cdf286321f70aef4ec9cb84236 Mon Sep 17 00:00:00 2001 From: AnvilaWang <98136112+AnvilaWang@users.noreply.github.com> Date: Fri, 18 Feb 2022 23:32:06 +0800 Subject: [PATCH] Add support for ZHAOXIN CPU (#218) --- include/cpuinfo_x86.h | 94 ++++++++++++++------------- src/impl_x86__base_implementation.inl | 49 +++++++++++++- 2 files changed, 97 insertions(+), 46 deletions(-) diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h index 69173a9..88daca4 100644 --- a/include/cpuinfo_x86.h +++ b/include/cpuinfo_x86.h @@ -25,6 +25,8 @@ CPU_FEATURES_START_CPP_NAMESPACE #define CPU_FEATURES_VENDOR_GENUINE_INTEL "GenuineIntel" #define CPU_FEATURES_VENDOR_AUTHENTIC_AMD "AuthenticAMD" #define CPU_FEATURES_VENDOR_HYGON_GENUINE "HygonGenuine" +#define CPU_FEATURES_VENDOR_CENTAUR_HAULS "CentaurHauls" +#define CPU_FEATURES_VENDOR_SHANGHAI " Shanghai " // See https://en.wikipedia.org/wiki/CPUID for a list of x86 cpu features. // The field names are based on the short name provided in the wikipedia tables. @@ -117,50 +119,54 @@ CacheInfo GetX86CacheInfo(void); typedef enum { X86_UNKNOWN, - INTEL_80486, // 80486 - INTEL_P5, // P5 - INTEL_LAKEMONT, // LAKEMONT - INTEL_CORE, // CORE - INTEL_PNR, // PENRYN - INTEL_NHM, // NEHALEM - INTEL_ATOM_BNL, // BONNELL - INTEL_WSM, // WESTMERE - INTEL_SNB, // SANDYBRIDGE - INTEL_IVB, // IVYBRIDGE - INTEL_ATOM_SMT, // SILVERMONT - INTEL_HSW, // HASWELL - INTEL_BDW, // BROADWELL - INTEL_SKL, // SKYLAKE - INTEL_ATOM_GMT, // GOLDMONT - INTEL_KBL, // KABY LAKE - INTEL_CFL, // COFFEE LAKE - INTEL_WHL, // WHISKEY LAKE - INTEL_CNL, // CANNON LAKE - INTEL_ICL, // ICE LAKE - INTEL_TGL, // TIGER LAKE - INTEL_SPR, // SAPPHIRE RAPIDS - INTEL_ADL, // ALDER LAKE - INTEL_RCL, // ROCKET LAKE - INTEL_KNIGHTS_M, // KNIGHTS MILL - INTEL_KNIGHTS_L, // KNIGHTS LANDING - INTEL_KNIGHTS_F, // KNIGHTS FERRY - INTEL_KNIGHTS_C, // KNIGHTS CORNER - INTEL_NETBURST, // NETBURST - AMD_HAMMER, // K8 HAMMER - AMD_K10, // K10 - AMD_K11, // K11 - AMD_K12, // K12 - AMD_BOBCAT, // K14 BOBCAT - AMD_PILEDRIVER, // K15 PILEDRIVER - AMD_STREAMROLLER, // K15 STREAMROLLER - AMD_EXCAVATOR, // K15 EXCAVATOR - AMD_BULLDOZER, // K15 BULLDOZER - AMD_JAGUAR, // K16 JAGUAR - AMD_PUMA, // K16 PUMA - AMD_ZEN, // K17 ZEN - AMD_ZEN_PLUS, // K17 ZEN+ - AMD_ZEN2, // K17 ZEN 2 - AMD_ZEN3, // K19 ZEN 3 + ZHAOXIN_ZHANGJIANG, // ZhangJiang + ZHAOXIN_WUDAOKOU, // WuDaoKou + ZHAOXIN_LUJIAZUI, // LuJiaZui + ZHAOXIN_YONGFENG, // YongFeng + INTEL_80486, // 80486 + INTEL_P5, // P5 + INTEL_LAKEMONT, // LAKEMONT + INTEL_CORE, // CORE + INTEL_PNR, // PENRYN + INTEL_NHM, // NEHALEM + INTEL_ATOM_BNL, // BONNELL + INTEL_WSM, // WESTMERE + INTEL_SNB, // SANDYBRIDGE + INTEL_IVB, // IVYBRIDGE + INTEL_ATOM_SMT, // SILVERMONT + INTEL_HSW, // HASWELL + INTEL_BDW, // BROADWELL + INTEL_SKL, // SKYLAKE + INTEL_ATOM_GMT, // GOLDMONT + INTEL_KBL, // KABY LAKE + INTEL_CFL, // COFFEE LAKE + INTEL_WHL, // WHISKEY LAKE + INTEL_CNL, // CANNON LAKE + INTEL_ICL, // ICE LAKE + INTEL_TGL, // TIGER LAKE + INTEL_SPR, // SAPPHIRE RAPIDS + INTEL_ADL, // ALDER LAKE + INTEL_RCL, // ROCKET LAKE + INTEL_KNIGHTS_M, // KNIGHTS MILL + INTEL_KNIGHTS_L, // KNIGHTS LANDING + INTEL_KNIGHTS_F, // KNIGHTS FERRY + INTEL_KNIGHTS_C, // KNIGHTS CORNER + INTEL_NETBURST, // NETBURST + AMD_HAMMER, // K8 HAMMER + AMD_K10, // K10 + AMD_K11, // K11 + AMD_K12, // K12 + AMD_BOBCAT, // K14 BOBCAT + AMD_PILEDRIVER, // K15 PILEDRIVER + AMD_STREAMROLLER, // K15 STREAMROLLER + AMD_EXCAVATOR, // K15 EXCAVATOR + AMD_BULLDOZER, // K15 BULLDOZER + AMD_JAGUAR, // K16 JAGUAR + AMD_PUMA, // K16 PUMA + AMD_ZEN, // K17 ZEN + AMD_ZEN_PLUS, // K17 ZEN+ + AMD_ZEN2, // K17 ZEN 2 + AMD_ZEN3, // K19 ZEN 3 X86_MICROARCHITECTURE_LAST_, } X86Microarchitecture; diff --git a/src/impl_x86__base_implementation.inl b/src/impl_x86__base_implementation.inl index e7991bd..09f24b2 100644 --- a/src/impl_x86__base_implementation.inl +++ b/src/impl_x86__base_implementation.inl @@ -406,8 +406,11 @@ X86Info GetX86Info(void) { IsVendor(leaves.leaf_0, CPU_FEATURES_VENDOR_AUTHENTIC_AMD); const bool is_hygon = IsVendor(leaves.leaf_0, CPU_FEATURES_VENDOR_HYGON_GENUINE); + const bool is_zhaoxin = + (IsVendor(leaves.leaf_0, CPU_FEATURES_VENDOR_CENTAUR_HAULS) || + IsVendor(leaves.leaf_0, CPU_FEATURES_VENDOR_SHANGHAI)); SetVendor(leaves.leaf_0, info.vendor); - if (is_intel || is_amd || is_hygon) { + if (is_intel || is_amd || is_hygon || is_zhaoxin) { OsPreserves os_preserves = kEmptyOsPreserves; ParseCpuId(&leaves, &info, &os_preserves); if (is_amd || is_hygon) { @@ -570,6 +573,42 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) { return X86_UNKNOWN; } } + if (IsVendorByX86Info(info, CPU_FEATURES_VENDOR_CENTAUR_HAULS)) { + switch (CPUID(info->family, info->model)) { + case CPUID(0x06, 0x0F): + case CPUID(0x06, 0x19): + // https://en.wikichip.org/wiki/zhaoxin/microarchitectures/zhangjiang + return ZHAOXIN_ZHANGJIANG; + case CPUID(0x07, 0x1B): + // https://en.wikichip.org/wiki/zhaoxin/microarchitectures/wudaokou + return ZHAOXIN_WUDAOKOU; + case CPUID(0x07, 0x3B): + // https://en.wikichip.org/wiki/zhaoxin/microarchitectures/lujiazui + return ZHAOXIN_LUJIAZUI; + case CPUID(0x07, 0x5B): + return ZHAOXIN_YONGFENG; + default: + return X86_UNKNOWN; + } + } + if (IsVendorByX86Info(info, CPU_FEATURES_VENDOR_SHANGHAI)) { + switch (CPUID(info->family, info->model)) { + case CPUID(0x06, 0x0F): + case CPUID(0x06, 0x19): + // https://en.wikichip.org/wiki/zhaoxin/microarchitectures/zhangjiang + return ZHAOXIN_ZHANGJIANG; + case CPUID(0x07, 0x1B): + // https://en.wikichip.org/wiki/zhaoxin/microarchitectures/wudaokou + return ZHAOXIN_WUDAOKOU; + case CPUID(0x07, 0x3B): + // https://en.wikichip.org/wiki/zhaoxin/microarchitectures/lujiazui + return ZHAOXIN_LUJIAZUI; + case CPUID(0x07, 0x5B): + return ZHAOXIN_YONGFENG; + default: + return X86_UNKNOWN; + } + } if (IsVendorByX86Info(info, CPU_FEATURES_VENDOR_AUTHENTIC_AMD)) { switch (CPUID(info->family, info->model)) { // https://en.wikichip.org/wiki/amd/cpuid @@ -1623,7 +1662,9 @@ static void ParseCacheInfo(const int max_cpuid_leaf, uint32_t leaf_id, CacheInfo GetX86CacheInfo(void) { CacheInfo info = kEmptyCacheInfo; const Leaves leaves = ReadLeaves(); - if (IsVendor(leaves.leaf_0, CPU_FEATURES_VENDOR_GENUINE_INTEL)) { + if (IsVendor(leaves.leaf_0, CPU_FEATURES_VENDOR_GENUINE_INTEL) || + IsVendor(leaves.leaf_0, CPU_FEATURES_VENDOR_CENTAUR_HAULS) || + IsVendor(leaves.leaf_0, CPU_FEATURES_VENDOR_SHANGHAI)) { ParseLeaf2(&leaves, &info); ParseCacheInfo(leaves.max_cpuid_leaf, 4, &info); } else if (IsVendor(leaves.leaf_0, CPU_FEATURES_VENDOR_AUTHENTIC_AMD) || @@ -1709,6 +1750,10 @@ CacheInfo GetX86CacheInfo(void) { #define X86_MICROARCHITECTURE_NAMES \ LINE(X86_UNKNOWN) \ + LINE(ZHAOXIN_ZHANGJIANG) \ + LINE(ZHAOXIN_WUDAOKOU) \ + LINE(ZHAOXIN_LUJIAZUI) \ + LINE(ZHAOXIN_YONGFENG) \ LINE(INTEL_80486) \ LINE(INTEL_P5) \ LINE(INTEL_LAKEMONT) \