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detect future Intel AVX/AMX features (#124)

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* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AVX512_BF16 and AVX512_VP2INTERSECT detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* correction for KNM features: s/4VBMI2/4FMAPS/g

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AMX/TMUL bits from 319433-040

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fixes #128
This commit is contained in:
Jeff Hammond
2020-09-21 00:56:26 -07:00
committed by GitHub
parent e698327713
commit 33bd72c1bc
3 changed files with 59 additions and 8 deletions
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2
test/cpuinfo_x86_test.cc
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@ -88,7 +88,7 @@ TEST(CpuidX86Test, SandyBridge) {
EXPECT_FALSE(features.avx512bitalg);
EXPECT_FALSE(features.avx512vpopcntdq);
EXPECT_FALSE(features.avx512_4vnniw);
EXPECT_FALSE(features.avx512_4vbmi2);
EXPECT_FALSE(features.avx512_4fmaps);
// All old cpu features should be set.
EXPECT_TRUE(features.aes);
EXPECT_TRUE(features.ssse3);