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https://github.com/google/cpu_features.git
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Add support for leaf2 and leaf4 on Intel's x86 arch (#80)
* Add support for leaf4 on Intel's x86 arch * Update cpuinfo_x86.h * Fix typo * Force compiler to use C99 * Add Intel x86 leaf2 support * Fixes after review * Fix review comments
This commit is contained in:
Artem Alekseev
committed by
Guillaume Chatelet
Guillaume Chatelet
parent
bfd109b687
commit
653d581e03
@ -70,9 +70,7 @@ uint32_t GetXCR0Eax(void) { return _xgetbv(0); }
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#error "Unsupported compiler, x86 cpuid requires either GCC, Clang or MSVC."
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#endif
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static Leaf CpuId(uint32_t leaf_id) {
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return CpuIdEx(leaf_id, 0);
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}
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static Leaf CpuId(uint32_t leaf_id) { return CpuIdEx(leaf_id, 0); }
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static const Leaf kEmptyLeaf;
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@ -131,6 +129,397 @@ static int IsVendor(const Leaf leaf, const char* const name) {
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return leaf.ebx == ebx && leaf.ecx == ecx && leaf.edx == edx;
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}
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static const CacheLevelInfo kEmptyCacheLevelInfo;
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static CacheLevelInfo MakeX86CacheLevelInfo(int level, CacheType cache_type,
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int cache_size, int ways,
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int line_size, int entries,
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int partitioning) {
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CacheLevelInfo info;
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info.level = level;
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info.cache_type = cache_type;
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info.cache_size = cache_size;
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info.ways = ways;
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info.line_size = line_size;
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info.tlb_entries = entries;
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info.partitioning = partitioning;
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return info;
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}
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static CacheLevelInfo GetCacheLevelInfo(const uint32_t reg) {
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const int UNDEF = -1;
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const int KiB = 1024;
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const int MiB = 1024 * KiB;
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const int GiB = 1024 * MiB;
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switch (reg) {
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case 0x01:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
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UNDEF, 32, 0);
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case 0x02:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * MiB, 0xFF,
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UNDEF, 2, 0);
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case 0x03:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
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UNDEF, 64, 0);
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case 0x04:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * MiB, 4,
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UNDEF, 8, 0);
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case 0x05:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * MiB, 4,
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UNDEF, 32, 0);
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case 0x06:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 8 * KiB, 4,
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32, UNDEF, 0);
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case 0x08:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 16 * KiB,
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4, 32, UNDEF, 0);
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case 0x09:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 32 * KiB,
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4, 64, UNDEF, 0);
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case 0x0A:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 8 * KiB, 2, 32,
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UNDEF, 0);
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case 0x0B:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * MiB, 4,
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UNDEF, 4, 0);
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case 0x0C:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 16 * KiB, 4, 32,
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UNDEF, 0);
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case 0x0D:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 16 * KiB, 4, 64,
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UNDEF, 0);
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case 0x0E:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 24 * KiB, 6, 64,
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UNDEF, 0);
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case 0x1D:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 128 * KiB, 2, 64,
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UNDEF, 0);
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case 0x21:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 256 * KiB, 8, 64,
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UNDEF, 0);
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case 0x22:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 512 * KiB, 4, 64,
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UNDEF, 2);
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case 0x23:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 1 * MiB, 8, 64,
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UNDEF, 2);
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case 0x24:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 16, 64,
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UNDEF, 0);
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case 0x25:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 2 * MiB, 8, 64,
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UNDEF, 2);
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case 0x29:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 4 * MiB, 8, 64,
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UNDEF, 2);
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case 0x2C:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 32 * KiB, 8, 64,
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UNDEF, 0);
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case 0x30:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 32 * KiB,
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8, 64, UNDEF, 0);
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case 0x40:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_DATA, UNDEF, UNDEF,
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UNDEF, UNDEF, 0);
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case 0x41:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 128 * KiB, 4, 32,
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UNDEF, 0);
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case 0x42:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 256 * KiB, 4, 32,
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UNDEF, 0);
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case 0x43:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 4, 32,
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UNDEF, 0);
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case 0x44:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 4, 32,
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UNDEF, 0);
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case 0x45:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 2 * MiB, 4, 32,
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UNDEF, 0);
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case 0x46:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 4 * MiB, 4, 64,
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UNDEF, 0);
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case 0x47:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 8 * MiB, 8, 64,
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UNDEF, 0);
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case 0x48:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 3 * MiB, 12, 64,
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UNDEF, 0);
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case 0x49:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 4 * MiB, 16, 64,
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UNDEF, 0);
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case (0x49 | (1 << 8)):
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 4 * MiB, 16, 64,
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UNDEF, 0);
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case 0x4A:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 6 * MiB, 12, 64,
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UNDEF, 0);
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case 0x4B:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 8 * MiB, 16, 64,
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UNDEF, 0);
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case 0x4C:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 12 * MiB, 12, 64,
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UNDEF, 0);
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case 0x4D:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 16 * MiB, 16, 64,
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UNDEF, 0);
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case 0x4E:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 6 * MiB, 24, 64,
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UNDEF, 0);
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case 0x4F:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
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UNDEF, 32, 0);
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case 0x50:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
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UNDEF, 64, 0);
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case 0x51:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
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UNDEF, 128, 0);
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case 0x52:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
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UNDEF, 256, 0);
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case 0x55:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 2 * MiB, 0xFF,
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UNDEF, 7, 0);
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case 0x56:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * MiB, 4,
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UNDEF, 16, 0);
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case 0x57:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
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UNDEF, 16, 0);
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case 0x59:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 0xFF,
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UNDEF, 16, 0);
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case 0x5A:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 2 * MiB, 4,
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UNDEF, 32, 0);
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case 0x5B:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
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UNDEF, 64, 0);
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case 0x5C:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
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UNDEF, 128, 0);
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case 0x5D:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4, UNDEF,
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UNDEF, 256, 0);
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case 0x60:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 16 * KiB, 8, 64,
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UNDEF, 0);
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case 0x61:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 0xFF,
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UNDEF, 48, 0);
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case 0x63:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 2 * MiB, 4,
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UNDEF, 4, 0);
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case 0x66:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 8 * KiB, 4, 64,
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UNDEF, 0);
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case 0x67:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 16 * KiB, 4, 64,
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UNDEF, 0);
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case 0x68:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 32 * KiB, 4, 64,
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UNDEF, 0);
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case 0x70:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 12 * KiB,
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8, UNDEF, UNDEF, 0);
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case 0x71:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 16 * KiB,
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8, UNDEF, UNDEF, 0);
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case 0x72:
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return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 32 * KiB,
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8, UNDEF, UNDEF, 0);
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case 0x76:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 2 * MiB, 0xFF,
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UNDEF, 8, 0);
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case 0x78:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 4, 64,
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UNDEF, 0);
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case 0x79:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 128 * KiB, 8, 64,
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UNDEF, 2);
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case 0x7A:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 256 * KiB, 8, 64,
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UNDEF, 2);
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case 0x7B:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 8, 64,
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UNDEF, 2);
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case 0x7C:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 8, 64,
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UNDEF, 2);
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case 0x7D:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 2 * MiB, 8, 64,
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UNDEF, 0);
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case 0x7F:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 2, 64,
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UNDEF, 0);
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case 0x80:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 8, 64,
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UNDEF, 0);
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case 0x82:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 256 * KiB, 8, 32,
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UNDEF, 0);
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case 0x83:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 8, 32,
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UNDEF, 0);
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case 0x84:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 8, 32,
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UNDEF, 0);
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case 0x85:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 2 * MiB, 8, 32,
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UNDEF, 0);
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case 0x86:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 4, 32,
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UNDEF, 0);
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case 0x87:
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return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 8, 64,
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UNDEF, 0);
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case 0xA0:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_DTLB, 4 * KiB, 0xFF,
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UNDEF, 32, 0);
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case 0xB0:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
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UNDEF, 128, 0);
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case 0xB1:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 2 * MiB, 4,
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UNDEF, 8, 0);
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case 0xB2:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
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UNDEF, 64, 0);
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case 0xB3:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
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UNDEF, 128, 0);
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case 0xB4:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
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UNDEF, 256, 0);
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case 0xB5:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 8,
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UNDEF, 64, 0);
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case 0xB6:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 8,
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UNDEF, 128, 0);
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case 0xBA:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
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UNDEF, 64, 0);
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case 0xC0:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
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UNDEF, 8, 0);
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case 0xC1:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_STLB, 4 * KiB, 8,
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UNDEF, 1024, 0);
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case 0xC2:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_DTLB, 4 * KiB, 4,
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UNDEF, 16, 0);
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case 0xC3:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_STLB, 4 * KiB, 6,
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UNDEF, 1536, 0);
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case 0xCA:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_STLB, 4 * KiB, 4,
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UNDEF, 512, 0);
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case 0xD0:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 512 * KiB, 4, 64,
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UNDEF, 0);
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case 0xD1:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 1 * MiB, 4, 64,
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UNDEF, 0);
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case 0xD2:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 2 * MiB, 4, 64,
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UNDEF, 0);
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case 0xD6:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 1 * MiB, 8, 64,
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UNDEF, 0);
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case 0xD7:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 2 * MiB, 8, 64,
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UNDEF, 0);
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case 0xD8:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 4 * MiB, 8, 64,
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UNDEF, 0);
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case 0xDC:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 1 * 1536 * KiB,
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12, 64, UNDEF, 0);
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case 0xDD:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 3 * MiB, 12, 64,
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UNDEF, 0);
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case 0xDE:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 6 * MiB, 12, 64,
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UNDEF, 0);
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case 0xE2:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 2 * MiB, 16, 64,
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UNDEF, 0);
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case 0xE3:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 4 * MiB, 16, 64,
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UNDEF, 0);
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case 0xE4:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 8 * MiB, 16, 64,
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UNDEF, 0);
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case 0xEA:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 12 * MiB, 24, 64,
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UNDEF, 0);
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case 0xEB:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 18 * MiB, 24, 64,
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UNDEF, 0);
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case 0xEC:
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return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 24 * MiB, 24, 64,
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UNDEF, 0);
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case 0xF0:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_PREFETCH, 64 * KiB,
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UNDEF, UNDEF, UNDEF, 0);
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case 0xF1:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_PREFETCH, 128 * KiB,
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UNDEF, UNDEF, UNDEF, 0);
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case 0xFF:
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return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_NULL, UNDEF, UNDEF,
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UNDEF, UNDEF, 0);
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default:
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return kEmptyCacheLevelInfo;
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}
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}
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static void GetByteArrayFromRegister(uint32_t result[4], const uint32_t reg) {
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for (int i = 0; i < 4; ++i) {
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result[i] = ExtractBitRange(reg, (i + 1) * 8, i * 8);
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}
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}
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static void ParseLeaf2(const int max_cpuid_leaf, CacheInfo* info) {
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Leaf leaf = SafeCpuId(max_cpuid_leaf, 2);
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uint32_t registers[] = {leaf.eax, leaf.ebx, leaf.ecx, leaf.edx};
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for (int i = 0; i < 4; ++i) {
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if (registers[i] & (1 << 31)) {
|
||||
continue; // register does not contains valid information
|
||||
}
|
||||
uint32_t bytes[4];
|
||||
GetByteArrayFromRegister(bytes, registers[i]);
|
||||
for (int i = 0; i < 4; ++i) {
|
||||
if (bytes[i] == 0xFF)
|
||||
break; // leaf 4 should be used to fetch cache information
|
||||
info->levels[info->size] = GetCacheLevelInfo(bytes[i]);
|
||||
}
|
||||
info->size++;
|
||||
}
|
||||
}
|
||||
|
||||
static void ParseLeaf4(const int max_cpuid_leaf, CacheInfo* info) {
|
||||
info->size = 0;
|
||||
for (int cache_id = 0; cache_id < CPU_FEATURES_MAX_CACHE_LEVEL; cache_id++) {
|
||||
const Leaf leaf = SafeCpuIdEx(max_cpuid_leaf, 4, cache_id);
|
||||
CacheType cache_type = ExtractBitRange(leaf.eax, 4, 0);
|
||||
if (cache_type == CPU_FEATURE_CACHE_NULL) {
|
||||
info->levels[cache_id] = kEmptyCacheLevelInfo;
|
||||
continue;
|
||||
}
|
||||
int level = ExtractBitRange(leaf.eax, 7, 5);
|
||||
int line_size = ExtractBitRange(leaf.ebx, 11, 0) + 1;
|
||||
int partitioning = ExtractBitRange(leaf.ebx, 21, 12) + 1;
|
||||
int ways = ExtractBitRange(leaf.ebx, 31, 22) + 1;
|
||||
int entries = leaf.ecx + 1;
|
||||
int cache_size = (ways * partitioning * line_size * (entries));
|
||||
info->levels[cache_id] = MakeX86CacheLevelInfo(
|
||||
level, cache_type, cache_size, ways, line_size, entries, partitioning);
|
||||
info->size++;
|
||||
}
|
||||
}
|
||||
|
||||
// Reference https://en.wikipedia.org/wiki/CPUID.
|
||||
static void ParseCpuId(const uint32_t max_cpuid_leaf, X86Info* info) {
|
||||
const Leaf leaf_1 = SafeCpuId(max_cpuid_leaf, 1);
|
||||
@ -217,6 +606,7 @@ static void ParseCpuId(const uint32_t max_cpuid_leaf, X86Info* info) {
|
||||
}
|
||||
|
||||
static const X86Info kEmptyX86Info;
|
||||
static const CacheInfo kEmptyCacheInfo;
|
||||
|
||||
X86Info GetX86Info(void) {
|
||||
X86Info info = kEmptyX86Info;
|
||||
@ -229,6 +619,17 @@ X86Info GetX86Info(void) {
|
||||
return info;
|
||||
}
|
||||
|
||||
CacheInfo GetX86CacheInfo(void) {
|
||||
CacheInfo info = kEmptyCacheInfo;
|
||||
const Leaf leaf_0 = CpuId(0);
|
||||
const uint32_t max_cpuid_leaf = leaf_0.eax;
|
||||
if (IsVendor(leaf_0, "GenuineIntel")) {
|
||||
ParseLeaf2(max_cpuid_leaf, &info);
|
||||
ParseLeaf4(max_cpuid_leaf, &info);
|
||||
}
|
||||
return info;
|
||||
}
|
||||
|
||||
#define CPUID(FAMILY, MODEL) ((((FAMILY)&0xFF) << 8) | ((MODEL)&0xFF))
|
||||
|
||||
X86Microarchitecture GetX86Microarchitecture(const X86Info* info) {
|
||||
|
||||
Reference in New Issue
Block a user