Add support for leaf2 and leaf4 on Intel's x86 arch (#80)

* Add support for leaf4 on Intel's x86 arch
* Update cpuinfo_x86.h
* Fix typo
* Force compiler to use C99
* Add Intel x86 leaf2 support
* Fixes after review
* Fix review comments

CMakeLists.txt

@@ -2,6 +2,8 @@ cmake_minimum_required(VERSION 3.0)
 
 project(CpuFeatures VERSION 0.1.0)
 
+set(CMAKE_C_STANDARD 99)
+
 # Default Build Type to be Release
 if(NOT CMAKE_BUILD_TYPE)
   set(CMAKE_BUILD_TYPE "Release" CACHE STRING

include/cpu_features_cache_info.h

@@ -0,0 +1,54 @@
+// Copyright 2017 Google Inc.
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//    http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef CPU_FEATURES_INCLUDE_CPUINFO_COMMON_H_
+#define CPU_FEATURES_INCLUDE_CPUINFO_COMMON_H_
+
+#include "cpu_features_macros.h"
+
+CPU_FEATURES_START_CPP_NAMESPACE
+
+typedef enum {
+  CPU_FEATURE_CACHE_NULL = 0,
+  CPU_FEATURE_CACHE_DATA = 1,
+  CPU_FEATURE_CACHE_INSTRUCTION = 2,
+  CPU_FEATURE_CACHE_UNIFIED = 3,
+  CPU_FEATURE_CACHE_TLB = 4,
+  CPU_FEATURE_CACHE_DTLB = 5,
+  CPU_FEATURE_CACHE_STLB = 6,
+  CPU_FEATURE_CACHE_PREFETCH = 7
+} CacheType;
+
+typedef struct {
+  int level;
+  CacheType cache_type;
+  int cache_size;    // Cache size in bytes
+  int ways;          // Associativity, 0 undefined, 0xFF fully associative
+  int line_size;     // Cache line size in bytes
+  int tlb_entries;   // number of entries for TLB
+  int partitioning;  // number of lines per sector
+} CacheLevelInfo;
+
+// Increase this value if more cache levels are needed.
+#ifndef CPU_FEATURES_MAX_CACHE_LEVEL
+#define CPU_FEATURES_MAX_CACHE_LEVEL 10
+#endif
+typedef struct {
+  int size;
+  CacheLevelInfo levels[CPU_FEATURES_MAX_CACHE_LEVEL];
+} CacheInfo;
+
+CPU_FEATURES_END_CPP_NAMESPACE
+
+#endif  // CPU_FEATURES_INCLUDE_CPUINFO_COMMON_H_

include/cpuinfo_aarch64.h

@@ -16,6 +16,7 @@
 #define CPU_FEATURES_INCLUDE_CPUINFO_AARCH64_H_
 
 #include "cpu_features_macros.h"
+#include "cpu_features_cache_info.h"
 
 CPU_FEATURES_START_CPP_NAMESPACE
 

include/cpuinfo_arm.h

@@ -17,6 +17,7 @@
 
 #include <stdint.h>  // uint32_t
 #include "cpu_features_macros.h"
+#include "cpu_features_cache_info.h"
 
 CPU_FEATURES_START_CPP_NAMESPACE
 

include/cpuinfo_mips.h

@@ -16,6 +16,7 @@
 #define CPU_FEATURES_INCLUDE_CPUINFO_MIPS_H_
 
 #include "cpu_features_macros.h"
+#include "cpu_features_cache_info.h"
 
 CPU_FEATURES_START_CPP_NAMESPACE
 

include/cpuinfo_ppc.h

@@ -16,6 +16,7 @@
 #define CPU_FEATURES_INCLUDE_CPUINFO_PPC_H_
 
 #include "cpu_features_macros.h"
+#include "cpu_features_cache_info.h"
 #include "internal/hwcaps.h"
 
 CPU_FEATURES_START_CPP_NAMESPACE

include/cpuinfo_x86.h

@@ -15,6 +15,7 @@
 #ifndef CPU_FEATURES_INCLUDE_CPUINFO_X86_H_
 #define CPU_FEATURES_INCLUDE_CPUINFO_X86_H_
 
+#include "cpu_features_cache_info.h"
 #include "cpu_features_macros.h"
 
 CPU_FEATURES_START_CPP_NAMESPACE
@@ -93,6 +94,12 @@ typedef struct {
 // This function is guaranteed to be malloc, memset and memcpy free.
 X86Info GetX86Info(void);
 
+// Returns cache hierarchy informations.
+// Can call cpuid multiple times.
+// Only works on Intel CPU at the moment.
+// This function is guaranteed to be malloc, memset and memcpy free.
+CacheInfo GetX86CacheInfo(void);
+
 typedef enum {
   X86_UNKNOWN,
   INTEL_CORE,      // CORE

src/cpuinfo_x86.c

@@ -70,9 +70,7 @@ uint32_t GetXCR0Eax(void) { return _xgetbv(0); }
 #error "Unsupported compiler, x86 cpuid requires either GCC, Clang or MSVC."
 #endif
 
-static Leaf CpuId(uint32_t leaf_id) {
+static Leaf CpuId(uint32_t leaf_id) { return CpuIdEx(leaf_id, 0); }
-  return CpuIdEx(leaf_id, 0);
-}
 
 static const Leaf kEmptyLeaf;
 
@@ -131,6 +129,397 @@ static int IsVendor(const Leaf leaf, const char* const name) {
   return leaf.ebx == ebx && leaf.ecx == ecx && leaf.edx == edx;
 }
 
+static const CacheLevelInfo kEmptyCacheLevelInfo;
+
+static CacheLevelInfo MakeX86CacheLevelInfo(int level, CacheType cache_type,
+                                            int cache_size, int ways,
+                                            int line_size, int entries,
+                                            int partitioning) {
+  CacheLevelInfo info;
+  info.level = level;
+  info.cache_type = cache_type;
+  info.cache_size = cache_size;
+  info.ways = ways;
+  info.line_size = line_size;
+  info.tlb_entries = entries;
+  info.partitioning = partitioning;
+  return info;
+}
+
+static CacheLevelInfo GetCacheLevelInfo(const uint32_t reg) {
+  const int UNDEF = -1;
+  const int KiB = 1024;
+  const int MiB = 1024 * KiB;
+  const int GiB = 1024 * MiB;
+  switch (reg) {
+    case 0x01:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
+                                   UNDEF, 32, 0);
+    case 0x02:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * MiB, 0xFF,
+                                   UNDEF, 2, 0);
+    case 0x03:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
+                                   UNDEF, 64, 0);
+    case 0x04:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * MiB, 4,
+                                   UNDEF, 8, 0);
+    case 0x05:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * MiB, 4,
+                                   UNDEF, 32, 0);
+    case 0x06:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 8 * KiB, 4,
+                                   32, UNDEF, 0);
+    case 0x08:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 16 * KiB,
+                                   4, 32, UNDEF, 0);
+    case 0x09:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 32 * KiB,
+                                   4, 64, UNDEF, 0);
+    case 0x0A:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 8 * KiB, 2, 32,
+                                   UNDEF, 0);
+    case 0x0B:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * MiB, 4,
+                                   UNDEF, 4, 0);
+    case 0x0C:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 16 * KiB, 4, 32,
+                                   UNDEF, 0);
+    case 0x0D:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 16 * KiB, 4, 64,
+                                   UNDEF, 0);
+    case 0x0E:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 24 * KiB, 6, 64,
+                                   UNDEF, 0);
+    case 0x1D:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 128 * KiB, 2, 64,
+                                   UNDEF, 0);
+    case 0x21:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 256 * KiB, 8, 64,
+                                   UNDEF, 0);
+    case 0x22:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 512 * KiB, 4, 64,
+                                   UNDEF, 2);
+    case 0x23:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 1 * MiB, 8, 64,
+                                   UNDEF, 2);
+    case 0x24:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 16, 64,
+                                   UNDEF, 0);
+    case 0x25:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 2 * MiB, 8, 64,
+                                   UNDEF, 2);
+    case 0x29:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 4 * MiB, 8, 64,
+                                   UNDEF, 2);
+    case 0x2C:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 32 * KiB, 8, 64,
+                                   UNDEF, 0);
+    case 0x30:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 32 * KiB,
+                                   8, 64, UNDEF, 0);
+    case 0x40:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_DATA, UNDEF, UNDEF,
+                                   UNDEF, UNDEF, 0);
+    case 0x41:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 128 * KiB, 4, 32,
+                                   UNDEF, 0);
+    case 0x42:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 256 * KiB, 4, 32,
+                                   UNDEF, 0);
+    case 0x43:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 4, 32,
+                                   UNDEF, 0);
+    case 0x44:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 4, 32,
+                                   UNDEF, 0);
+    case 0x45:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 2 * MiB, 4, 32,
+                                   UNDEF, 0);
+    case 0x46:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 4 * MiB, 4, 64,
+                                   UNDEF, 0);
+    case 0x47:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 8 * MiB, 8, 64,
+                                   UNDEF, 0);
+    case 0x48:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 3 * MiB, 12, 64,
+                                   UNDEF, 0);
+    case 0x49:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 4 * MiB, 16, 64,
+                                   UNDEF, 0);
+    case (0x49 | (1 << 8)):
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 4 * MiB, 16, 64,
+                                   UNDEF, 0);
+    case 0x4A:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 6 * MiB, 12, 64,
+                                   UNDEF, 0);
+    case 0x4B:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 8 * MiB, 16, 64,
+                                   UNDEF, 0);
+    case 0x4C:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 12 * MiB, 12, 64,
+                                   UNDEF, 0);
+    case 0x4D:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 16 * MiB, 16, 64,
+                                   UNDEF, 0);
+    case 0x4E:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 6 * MiB, 24, 64,
+                                   UNDEF, 0);
+    case 0x4F:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
+                                   UNDEF, 32, 0);
+    case 0x50:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
+                                   UNDEF, 64, 0);
+    case 0x51:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
+                                   UNDEF, 128, 0);
+    case 0x52:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
+                                   UNDEF, 256, 0);
+    case 0x55:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 2 * MiB, 0xFF,
+                                   UNDEF, 7, 0);
+    case 0x56:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * MiB, 4,
+                                   UNDEF, 16, 0);
+    case 0x57:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
+                                   UNDEF, 16, 0);
+    case 0x59:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 0xFF,
+                                   UNDEF, 16, 0);
+    case 0x5A:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 2 * MiB, 4,
+                                   UNDEF, 32, 0);
+    case 0x5B:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
+                                   UNDEF, 64, 0);
+    case 0x5C:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, UNDEF,
+                                   UNDEF, 128, 0);
+    case 0x5D:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4, UNDEF,
+                                   UNDEF, 256, 0);
+    case 0x60:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 16 * KiB, 8, 64,
+                                   UNDEF, 0);
+    case 0x61:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 0xFF,
+                                   UNDEF, 48, 0);
+    case 0x63:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 2 * MiB, 4,
+                                   UNDEF, 4, 0);
+    case 0x66:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 8 * KiB, 4, 64,
+                                   UNDEF, 0);
+    case 0x67:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 16 * KiB, 4, 64,
+                                   UNDEF, 0);
+    case 0x68:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_DATA, 32 * KiB, 4, 64,
+                                   UNDEF, 0);
+    case 0x70:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 12 * KiB,
+                                   8, UNDEF, UNDEF, 0);
+    case 0x71:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 16 * KiB,
+                                   8, UNDEF, UNDEF, 0);
+    case 0x72:
+      return MakeX86CacheLevelInfo(1, CPU_FEATURE_CACHE_INSTRUCTION, 32 * KiB,
+                                   8, UNDEF, UNDEF, 0);
+    case 0x76:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 2 * MiB, 0xFF,
+                                   UNDEF, 8, 0);
+    case 0x78:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 4, 64,
+                                   UNDEF, 0);
+    case 0x79:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 128 * KiB, 8, 64,
+                                   UNDEF, 2);
+    case 0x7A:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 256 * KiB, 8, 64,
+                                   UNDEF, 2);
+    case 0x7B:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 8, 64,
+                                   UNDEF, 2);
+    case 0x7C:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 8, 64,
+                                   UNDEF, 2);
+    case 0x7D:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 2 * MiB, 8, 64,
+                                   UNDEF, 0);
+    case 0x7F:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 2, 64,
+                                   UNDEF, 0);
+    case 0x80:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 8, 64,
+                                   UNDEF, 0);
+    case 0x82:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 256 * KiB, 8, 32,
+                                   UNDEF, 0);
+    case 0x83:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 8, 32,
+                                   UNDEF, 0);
+    case 0x84:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 8, 32,
+                                   UNDEF, 0);
+    case 0x85:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 2 * MiB, 8, 32,
+                                   UNDEF, 0);
+    case 0x86:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 512 * KiB, 4, 32,
+                                   UNDEF, 0);
+    case 0x87:
+      return MakeX86CacheLevelInfo(2, CPU_FEATURE_CACHE_DATA, 1 * MiB, 8, 64,
+                                   UNDEF, 0);
+    case 0xA0:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_DTLB, 4 * KiB, 0xFF,
+                                   UNDEF, 32, 0);
+    case 0xB0:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
+                                   UNDEF, 128, 0);
+    case 0xB1:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 2 * MiB, 4,
+                                   UNDEF, 8, 0);
+    case 0xB2:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
+                                   UNDEF, 64, 0);
+    case 0xB3:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
+                                   UNDEF, 128, 0);
+    case 0xB4:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
+                                   UNDEF, 256, 0);
+    case 0xB5:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 8,
+                                   UNDEF, 64, 0);
+    case 0xB6:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 8,
+                                   UNDEF, 128, 0);
+    case 0xBA:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
+                                   UNDEF, 64, 0);
+    case 0xC0:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_TLB, 4 * KiB, 4,
+                                   UNDEF, 8, 0);
+    case 0xC1:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_STLB, 4 * KiB, 8,
+                                   UNDEF, 1024, 0);
+    case 0xC2:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_DTLB, 4 * KiB, 4,
+                                   UNDEF, 16, 0);
+    case 0xC3:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_STLB, 4 * KiB, 6,
+                                   UNDEF, 1536, 0);
+    case 0xCA:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_STLB, 4 * KiB, 4,
+                                   UNDEF, 512, 0);
+    case 0xD0:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 512 * KiB, 4, 64,
+                                   UNDEF, 0);
+    case 0xD1:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 1 * MiB, 4, 64,
+                                   UNDEF, 0);
+    case 0xD2:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 2 * MiB, 4, 64,
+                                   UNDEF, 0);
+    case 0xD6:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 1 * MiB, 8, 64,
+                                   UNDEF, 0);
+    case 0xD7:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 2 * MiB, 8, 64,
+                                   UNDEF, 0);
+    case 0xD8:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 4 * MiB, 8, 64,
+                                   UNDEF, 0);
+    case 0xDC:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 1 * 1536 * KiB,
+                                   12, 64, UNDEF, 0);
+    case 0xDD:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 3 * MiB, 12, 64,
+                                   UNDEF, 0);
+    case 0xDE:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 6 * MiB, 12, 64,
+                                   UNDEF, 0);
+    case 0xE2:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 2 * MiB, 16, 64,
+                                   UNDEF, 0);
+    case 0xE3:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 4 * MiB, 16, 64,
+                                   UNDEF, 0);
+    case 0xE4:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 8 * MiB, 16, 64,
+                                   UNDEF, 0);
+    case 0xEA:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 12 * MiB, 24, 64,
+                                   UNDEF, 0);
+    case 0xEB:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 18 * MiB, 24, 64,
+                                   UNDEF, 0);
+    case 0xEC:
+      return MakeX86CacheLevelInfo(3, CPU_FEATURE_CACHE_DATA, 24 * MiB, 24, 64,
+                                   UNDEF, 0);
+    case 0xF0:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_PREFETCH, 64 * KiB,
+                                   UNDEF, UNDEF, UNDEF, 0);
+    case 0xF1:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_PREFETCH, 128 * KiB,
+                                   UNDEF, UNDEF, UNDEF, 0);
+    case 0xFF:
+      return MakeX86CacheLevelInfo(UNDEF, CPU_FEATURE_CACHE_NULL, UNDEF, UNDEF,
+                                   UNDEF, UNDEF, 0);
+    default:
+      return kEmptyCacheLevelInfo;
+  }
+}
+
+static void GetByteArrayFromRegister(uint32_t result[4], const uint32_t reg) {
+  for (int i = 0; i < 4; ++i) {
+    result[i] = ExtractBitRange(reg, (i + 1) * 8, i * 8);
+  }
+}
+
+static void ParseLeaf2(const int max_cpuid_leaf, CacheInfo* info) {
+  Leaf leaf = SafeCpuId(max_cpuid_leaf, 2);
+  uint32_t registers[] = {leaf.eax, leaf.ebx, leaf.ecx, leaf.edx};
+  for (int i = 0; i < 4; ++i) {
+    if (registers[i] & (1 << 31)) {
+      continue;  // register does not contains valid information
+    }
+    uint32_t bytes[4];
+    GetByteArrayFromRegister(bytes, registers[i]);
+    for (int i = 0; i < 4; ++i) {
+      if (bytes[i] == 0xFF)
+        break;  // leaf 4 should be used to fetch cache information
+      info->levels[info->size] = GetCacheLevelInfo(bytes[i]);
+    }
+    info->size++;
+  }
+}
+
+static void ParseLeaf4(const int max_cpuid_leaf, CacheInfo* info) {
+  info->size = 0;
+  for (int cache_id = 0; cache_id < CPU_FEATURES_MAX_CACHE_LEVEL; cache_id++) {
+    const Leaf leaf = SafeCpuIdEx(max_cpuid_leaf, 4, cache_id);
+    CacheType cache_type = ExtractBitRange(leaf.eax, 4, 0);
+    if (cache_type == CPU_FEATURE_CACHE_NULL) {
+      info->levels[cache_id] = kEmptyCacheLevelInfo;
+      continue;
+    }
+    int level = ExtractBitRange(leaf.eax, 7, 5);
+    int line_size = ExtractBitRange(leaf.ebx, 11, 0) + 1;
+    int partitioning = ExtractBitRange(leaf.ebx, 21, 12) + 1;
+    int ways = ExtractBitRange(leaf.ebx, 31, 22) + 1;
+    int entries = leaf.ecx + 1;
+    int cache_size = (ways * partitioning * line_size * (entries));
+    info->levels[cache_id] = MakeX86CacheLevelInfo(
+        level, cache_type, cache_size, ways, line_size, entries, partitioning);
+    info->size++;
+  }
+}
+
 // Reference https://en.wikipedia.org/wiki/CPUID.
 static void ParseCpuId(const uint32_t max_cpuid_leaf, X86Info* info) {
   const Leaf leaf_1 = SafeCpuId(max_cpuid_leaf, 1);
@@ -217,6 +606,7 @@ static void ParseCpuId(const uint32_t max_cpuid_leaf, X86Info* info) {
 }
 
 static const X86Info kEmptyX86Info;
+static const CacheInfo kEmptyCacheInfo;
 
 X86Info GetX86Info(void) {
   X86Info info = kEmptyX86Info;
@@ -229,6 +619,17 @@ X86Info GetX86Info(void) {
   return info;
 }
 
+CacheInfo GetX86CacheInfo(void) {
+  CacheInfo info = kEmptyCacheInfo;
+  const Leaf leaf_0 = CpuId(0);
+  const uint32_t max_cpuid_leaf = leaf_0.eax;
+  if (IsVendor(leaf_0, "GenuineIntel")) {
+    ParseLeaf2(max_cpuid_leaf, &info);
+    ParseLeaf4(max_cpuid_leaf, &info);
+  }
+  return info;
+}
+
 #define CPUID(FAMILY, MODEL) ((((FAMILY)&0xFF) << 8) | ((MODEL)&0xFF))
 
 X86Microarchitecture GetX86Microarchitecture(const X86Info* info) {

test/cpuinfo_x86_test.cc

@@ -26,14 +26,16 @@ namespace cpu_features {
 class FakeCpu {
  public:
   Leaf CpuIdEx(uint32_t leaf_id, int ecx) const {
-    const auto itr = cpuid_leaves_.find(leaf_id);
+    const auto itr = cpuid_leaves_.find(std::make_pair(leaf_id, ecx));
-    EXPECT_TRUE(itr != cpuid_leaves_.end()) << "Missing leaf " << leaf_id;
+    if (itr != cpuid_leaves_.end()) {
       return itr->second;
     }
+    return {0, 0, 0, 0};
+  }
 
   uint32_t GetXCR0Eax() const { return xcr0_eax_; }
 
-  void SetLeaves(std::map<uint32_t, Leaf> configuration) {
+  void SetLeaves(std::map<std::pair<uint32_t, int>, Leaf> configuration) {
     cpuid_leaves_ = std::move(configuration);
   }
 
@@ -42,13 +44,15 @@ class FakeCpu {
   }
 
  private:
-  std::map<uint32_t, Leaf> cpuid_leaves_;
+  std::map<std::pair<uint32_t, int>, Leaf> cpuid_leaves_;
   uint32_t xcr0_eax_;
 };
 
 auto* g_fake_cpu = new FakeCpu();
 
-extern "C" Leaf CpuIdEx(uint32_t leaf_id, int ecx) { return g_fake_cpu->CpuIdEx(leaf_id, ecx); }
+extern "C" Leaf CpuIdEx(uint32_t leaf_id, int ecx) {
+  return g_fake_cpu->CpuIdEx(leaf_id, ecx);
+}
 
 extern "C" uint32_t GetXCR0Eax(void) { return g_fake_cpu->GetXCR0Eax(); }
 
@@ -57,9 +61,9 @@ namespace {
 TEST(CpuidX86Test, SandyBridge) {
   g_fake_cpu->SetOsBackupsExtendedRegisters(true);
   g_fake_cpu->SetLeaves({
-      {0x00000000, Leaf{0x0000000D, 0x756E6547, 0x6C65746E, 0x49656E69}},
+      {{0x00000000, 0}, Leaf{0x0000000D, 0x756E6547, 0x6C65746E, 0x49656E69}},
-      {0x00000001, Leaf{0x000206A6, 0x00100800, 0x1F9AE3BF, 0xBFEBFBFF}},
+      {{0x00000001, 0}, Leaf{0x000206A6, 0x00100800, 0x1F9AE3BF, 0xBFEBFBFF}},
-      {0x00000007, Leaf{0x00000000, 0x00000000, 0x00000000, 0x00000000}},
+      {{0x00000007, 0}, Leaf{0x00000000, 0x00000000, 0x00000000, 0x00000000}},
   });
   const auto info = GetX86Info();
   EXPECT_STREQ(info.vendor, "GenuineIntel");
@@ -97,11 +101,14 @@ TEST(CpuidX86Test, SandyBridge) {
   EXPECT_FALSE(features.rdrnd);
 }
 
+const int KiB = 1024;
+const int MiB = 1024 * KiB;
+
 TEST(CpuidX86Test, SandyBridgeTestOsSupport) {
   g_fake_cpu->SetLeaves({
-      {0x00000000, Leaf{0x0000000D, 0x756E6547, 0x6C65746E, 0x49656E69}},
+      {{0x00000000, 0}, Leaf{0x0000000D, 0x756E6547, 0x6C65746E, 0x49656E69}},
-      {0x00000001, Leaf{0x000206A6, 0x00100800, 0x1F9AE3BF, 0xBFEBFBFF}},
+      {{0x00000001, 0}, Leaf{0x000206A6, 0x00100800, 0x1F9AE3BF, 0xBFEBFBFF}},
-      {0x00000007, Leaf{0x00000000, 0x00000000, 0x00000000, 0x00000000}},
+      {{0x00000007, 0}, Leaf{0x00000000, 0x00000000, 0x00000000, 0x00000000}},
   });
   // avx is disabled if os does not support backing up ymm registers.
   g_fake_cpu->SetOsBackupsExtendedRegisters(false);
@@ -114,9 +121,9 @@ TEST(CpuidX86Test, SandyBridgeTestOsSupport) {
 TEST(CpuidX86Test, SkyLake) {
   g_fake_cpu->SetOsBackupsExtendedRegisters(true);
   g_fake_cpu->SetLeaves({
-      {0x00000000, Leaf{0x00000016, 0x756E6547, 0x6C65746E, 0x49656E69}},
+      {{0x00000000, 0}, Leaf{0x00000016, 0x756E6547, 0x6C65746E, 0x49656E69}},
-      {0x00000001, Leaf{0x000406E3, 0x00100800, 0x7FFAFBBF, 0xBFEBFBFF}},
+      {{0x00000001, 0}, Leaf{0x000406E3, 0x00100800, 0x7FFAFBBF, 0xBFEBFBFF}},
-      {0x00000007, Leaf{0x00000000, 0x029C67AF, 0x00000000, 0x00000000}},
+      {{0x00000007, 0}, Leaf{0x00000000, 0x029C67AF, 0x00000000, 0x00000000}},
   });
   const auto info = GetX86Info();
   EXPECT_STREQ(info.vendor, "GenuineIntel");
@@ -128,32 +135,129 @@ TEST(CpuidX86Test, SkyLake) {
 
 TEST(CpuidX86Test, Branding) {
   g_fake_cpu->SetLeaves({
-      {0x00000000, Leaf{0x00000016, 0x756E6547, 0x6C65746E, 0x49656E69}},
+      {{0x00000000, 0}, Leaf{0x00000016, 0x756E6547, 0x6C65746E, 0x49656E69}},
-      {0x00000001, Leaf{0x000406E3, 0x00100800, 0x7FFAFBBF, 0xBFEBFBFF}},
+      {{0x00000001, 0}, Leaf{0x000406E3, 0x00100800, 0x7FFAFBBF, 0xBFEBFBFF}},
-      {0x00000007, Leaf{0x00000000, 0x029C67AF, 0x00000000, 0x00000000}},
+      {{0x00000007, 0}, Leaf{0x00000000, 0x029C67AF, 0x00000000, 0x00000000}},
-      {0x80000000, Leaf{0x80000008, 0x00000000, 0x00000000, 0x00000000}},
+      {{0x80000000, 0}, Leaf{0x80000008, 0x00000000, 0x00000000, 0x00000000}},
-      {0x80000001, Leaf{0x00000000, 0x00000000, 0x00000121, 0x2C100000}},
+      {{0x80000001, 0}, Leaf{0x00000000, 0x00000000, 0x00000121, 0x2C100000}},
-      {0x80000002, Leaf{0x65746E49, 0x2952286C, 0x726F4320, 0x4D542865}},
+      {{0x80000002, 0}, Leaf{0x65746E49, 0x2952286C, 0x726F4320, 0x4D542865}},
-      {0x80000003, Leaf{0x37692029, 0x3035362D, 0x43205530, 0x40205550}},
+      {{0x80000003, 0}, Leaf{0x37692029, 0x3035362D, 0x43205530, 0x40205550}},
-      {0x80000004, Leaf{0x352E3220, 0x7A484730, 0x00000000, 0x00000000}},
+      {{0x80000004, 0}, Leaf{0x352E3220, 0x7A484730, 0x00000000, 0x00000000}},
   });
   char brand_string[49];
   FillX86BrandString(brand_string);
   EXPECT_STREQ(brand_string, "Intel(R) Core(TM) i7-6500U CPU @ 2.50GHz");
 }
 
+TEST(CpuidX86Test, KabyLakeCache) {
+  g_fake_cpu->SetLeaves({
+      {{0x00000000, 0}, Leaf{0x00000016, 0x756E6547, 0x6C65746E, 0x49656E69}},
+      {{0x00000001, 0}, Leaf{0x000406E3, 0x00100800, 0x7FFAFBBF, 0xBFEBFBFF}},
+      {{0x00000004, 0}, Leaf{0x1C004121, 0x01C0003F, 0x0000003F, 0x00000000}},
+      {{0x00000004, 1}, Leaf{0x1C004122, 0x01C0003F, 0x0000003F, 0x00000000}},
+      {{0x00000004, 2}, Leaf{0x1C004143, 0x00C0003F, 0x000003FF, 0x00000000}},
+      {{0x00000004, 3}, Leaf{0x1C03C163, 0x02C0003F, 0x00001FFF, 0x00000002}},
+      {{0x00000007, 0}, Leaf{0x00000000, 0x029C67AF, 0x00000000, 0x00000000}},
+      {{0x80000000, 0}, Leaf{0x80000008, 0x00000000, 0x00000000, 0x00000000}},
+      {{0x80000001, 0}, Leaf{0x00000000, 0x00000000, 0x00000121, 0x2C100000}},
+      {{0x80000002, 0}, Leaf{0x65746E49, 0x2952286C, 0x726F4320, 0x4D542865}},
+      {{0x80000003, 0}, Leaf{0x37692029, 0x3035362D, 0x43205530, 0x40205550}},
+  });
+  const auto info = GetX86CacheInfo();
+  EXPECT_EQ(info.size, 4);
+  EXPECT_EQ(info.levels[0].level, 1);
+  EXPECT_EQ(info.levels[0].cache_type, 1);
+  EXPECT_EQ(info.levels[0].cache_size, 32 * KiB);
+  EXPECT_EQ(info.levels[0].ways, 8);
+  EXPECT_EQ(info.levels[0].line_size, 64);
+  EXPECT_EQ(info.levels[0].tlb_entries, 64);
+  EXPECT_EQ(info.levels[0].partitioning, 1);
+
+  EXPECT_EQ(info.levels[1].level, 1);
+  EXPECT_EQ(info.levels[1].cache_type, 2);
+  EXPECT_EQ(info.levels[1].cache_size, 32 * KiB);
+  EXPECT_EQ(info.levels[1].ways, 8);
+  EXPECT_EQ(info.levels[1].line_size, 64);
+  EXPECT_EQ(info.levels[1].tlb_entries, 64);
+  EXPECT_EQ(info.levels[1].partitioning, 1);
+
+  EXPECT_EQ(info.levels[2].level, 2);
+  EXPECT_EQ(info.levels[2].cache_type, 3);
+  EXPECT_EQ(info.levels[2].cache_size, 256 * KiB);
+  EXPECT_EQ(info.levels[2].ways, 4);
+  EXPECT_EQ(info.levels[2].line_size, 64);
+  EXPECT_EQ(info.levels[2].tlb_entries, 1024);
+  EXPECT_EQ(info.levels[2].partitioning, 1);
+
+  EXPECT_EQ(info.levels[3].level, 3);
+  EXPECT_EQ(info.levels[3].cache_type, 3);
+  EXPECT_EQ(info.levels[3].cache_size, 6 * MiB);
+  EXPECT_EQ(info.levels[3].ways, 12);
+  EXPECT_EQ(info.levels[3].line_size, 64);
+  EXPECT_EQ(info.levels[3].tlb_entries, 8192);
+  EXPECT_EQ(info.levels[3].partitioning, 1);
+}
+
+TEST(CpuidX86Test, HSWCache) {
+  g_fake_cpu->SetLeaves({
+      {{0x00000000, 0}, Leaf{0x00000016, 0x756E6547, 0x6C65746E, 0x49656E69}},
+      {{0x00000001, 0}, Leaf{0x000406E3, 0x00100800, 0x7FFAFBBF, 0xBFEBFBFF}},
+      {{0x00000004, 0}, Leaf{0x1C004121, 0x01C0003F, 0x0000003F, 0x00000000}},
+      {{0x00000004, 1}, Leaf{0x1C004122, 0x01C0003F, 0x0000003F, 0x00000000}},
+      {{0x00000004, 2}, Leaf{0x1C004143, 0x01C0003F, 0x000001FF, 0x00000000}},
+      {{0x00000004, 3}, Leaf{0x1C03C163, 0x02C0003F, 0x00001FFF, 0x00000006}},
+      {{0x00000007, 0}, Leaf{0x00000000, 0x029C67AF, 0x00000000, 0x00000000}},
+      {{0x80000000, 0}, Leaf{0x80000008, 0x00000000, 0x00000000, 0x00000000}},
+      {{0x80000001, 0}, Leaf{0x00000000, 0x00000000, 0x00000121, 0x2C100000}},
+      {{0x80000002, 0}, Leaf{0x65746E49, 0x2952286C, 0x726F4320, 0x4D542865}},
+      {{0x80000003, 0}, Leaf{0x37692029, 0x3035362D, 0x43205530, 0x40205550}},
+  });
+  const auto info = GetX86CacheInfo();
+  EXPECT_EQ(info.size, 4);
+  EXPECT_EQ(info.levels[0].level, 1);
+  EXPECT_EQ(info.levels[0].cache_type, 1);
+  EXPECT_EQ(info.levels[0].cache_size, 32 * KiB);
+  EXPECT_EQ(info.levels[0].ways, 8);
+  EXPECT_EQ(info.levels[0].line_size, 64);
+  EXPECT_EQ(info.levels[0].tlb_entries, 64);
+  EXPECT_EQ(info.levels[0].partitioning, 1);
+
+  EXPECT_EQ(info.levels[1].level, 1);
+  EXPECT_EQ(info.levels[1].cache_type, 2);
+  EXPECT_EQ(info.levels[1].cache_size, 32 * KiB);
+  EXPECT_EQ(info.levels[1].ways, 8);
+  EXPECT_EQ(info.levels[1].line_size, 64);
+  EXPECT_EQ(info.levels[1].tlb_entries, 64);
+  EXPECT_EQ(info.levels[1].partitioning, 1);
+
+  EXPECT_EQ(info.levels[2].level, 2);
+  EXPECT_EQ(info.levels[2].cache_type, 3);
+  EXPECT_EQ(info.levels[2].cache_size, 256 * KiB);
+  EXPECT_EQ(info.levels[2].ways, 8);
+  EXPECT_EQ(info.levels[2].line_size, 64);
+  EXPECT_EQ(info.levels[2].tlb_entries, 512);
+  EXPECT_EQ(info.levels[2].partitioning, 1);
+
+  EXPECT_EQ(info.levels[3].level, 3);
+  EXPECT_EQ(info.levels[3].cache_type, 3);
+  EXPECT_EQ(info.levels[3].cache_size, 6 * MiB);
+  EXPECT_EQ(info.levels[3].ways, 12);
+  EXPECT_EQ(info.levels[3].line_size, 64);
+  EXPECT_EQ(info.levels[3].tlb_entries, 8192);
+  EXPECT_EQ(info.levels[3].partitioning, 1);
+}
 // http://users.atw.hu/instlatx64/AuthenticAMD0630F81_K15_Godavari_CPUID.txt
 TEST(CpuidX86Test, AMD_K15) {
   g_fake_cpu->SetLeaves({
-      {0x00000000, Leaf{0x0000000D, 0x68747541, 0x444D4163, 0x69746E65}},
+      {{0x00000000, 0}, Leaf{0x0000000D, 0x68747541, 0x444D4163, 0x69746E65}},
-      {0x00000001, Leaf{0x00630F81, 0x00040800, 0x3E98320B, 0x178BFBFF}},
+      {{0x00000001, 0}, Leaf{0x00630F81, 0x00040800, 0x3E98320B, 0x178BFBFF}},
-      {0x00000007, Leaf{0x00000000, 0x00000000, 0x00000000, 0x00000000}},
+      {{0x00000007, 0}, Leaf{0x00000000, 0x00000000, 0x00000000, 0x00000000}},
-      {0x80000000, Leaf{0x8000001E, 0x68747541, 0x444D4163, 0x69746E65}},
+      {{0x80000000, 0}, Leaf{0x8000001E, 0x68747541, 0x444D4163, 0x69746E65}},
-      {0x80000001, Leaf{0x00630F81, 0x10000000, 0x0FEBBFFF, 0x2FD3FBFF}},
+      {{0x80000001, 0}, Leaf{0x00630F81, 0x10000000, 0x0FEBBFFF, 0x2FD3FBFF}},
-      {0x80000002, Leaf{0x20444D41, 0x372D3841, 0x4B303736, 0x64615220}},
+      {{0x80000002, 0}, Leaf{0x20444D41, 0x372D3841, 0x4B303736, 0x64615220}},
-      {0x80000003, Leaf{0x206E6F65, 0x202C3752, 0x43203031, 0x75706D6F}},
+      {{0x80000003, 0}, Leaf{0x206E6F65, 0x202C3752, 0x43203031, 0x75706D6F}},
-      {0x80000004, Leaf{0x43206574, 0x7365726F, 0x2B433420, 0x00204736}},
+      {{0x80000004, 0}, Leaf{0x43206574, 0x7365726F, 0x2B433420, 0x00204736}},
-      {0x80000005, Leaf{0xFF40FF18, 0xFF40FF30, 0x10040140, 0x60030140}},
+      {{0x80000005, 0}, Leaf{0xFF40FF18, 0xFF40FF30, 0x10040140, 0x60030140}},
   });
   const auto info = GetX86Info();