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add intel Tremont microarch

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Andrew Kurushin 2022-08-02 18:14:55 +03:00 committed by Mizux
parent f60b6f8405
commit 6d62f2fa64
3 changed files with 34 additions and 0 deletions
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1
include/cpuinfo_x86.h
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@ -139,6 +139,7 @@ typedef enum {
INTEL_BDW, // BROADWELL INTEL_BDW, // BROADWELL
INTEL_SKL, // SKYLAKE INTEL_SKL, // SKYLAKE
INTEL_ATOM_GMT, // GOLDMONT INTEL_ATOM_GMT, // GOLDMONT
INTEL_ATOM_TMT, // TREMONT
INTEL_KBL, // KABY LAKE INTEL_KBL, // KABY LAKE
INTEL_CFL, // COFFEE LAKE INTEL_CFL, // COFFEE LAKE
INTEL_WHL, // WHISKEY LAKE INTEL_WHL, // WHISKEY LAKE

5
src/impl_x86__base_implementation.inl
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@ -465,6 +465,10 @@ X86Microarchitecture GetX86Microarchitecture(const X86Info* info) {
case CPUID(0x06, 0x5C): case CPUID(0x06, 0x5C):
// https://en.wikipedia.org/wiki/Goldmont // https://en.wikipedia.org/wiki/Goldmont
return INTEL_ATOM_GMT; return INTEL_ATOM_GMT;
case CPUID(0x06, 0x96):
case CPUID(0x06, 0x9C):
// https://en.wikichip.org/wiki/intel/microarchitectures/tremont
return INTEL_ATOM_TMT;
case CPUID(0x06, 0x0F): case CPUID(0x06, 0x0F):
case CPUID(0x06, 0x16): case CPUID(0x06, 0x16):
// https://en.wikipedia.org/wiki/Intel_Core_(microarchitecture) // https://en.wikipedia.org/wiki/Intel_Core_(microarchitecture)
@ -1784,6 +1788,7 @@ CacheInfo GetX86CacheInfo(void) {
LINE(INTEL_BDW) \ LINE(INTEL_BDW) \
LINE(INTEL_SKL) \ LINE(INTEL_SKL) \
LINE(INTEL_ATOM_GMT) \ LINE(INTEL_ATOM_GMT) \
LINE(INTEL_ATOM_TMT) \
LINE(INTEL_KBL) \ LINE(INTEL_KBL) \
LINE(INTEL_CFL) \ LINE(INTEL_CFL) \
LINE(INTEL_WHL) \ LINE(INTEL_WHL) \

28
test/cpuinfo_x86_test.cc
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@ -1172,6 +1172,34 @@ TEST_F(CpuidX86Test, INTEL_CML_H) {
EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_CML); EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_CML);
} }
// https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel00906C0_JasperLake_01_CPUID.txt
TEST_F(CpuidX86Test, INTEL_ATOM_TMT_JASPER_LAKE) {
cpu().SetLeaves({
{{0x00000000, 0}, Leaf{0x0000001B, 0x756E6547, 0x6C65746E, 0x49656E69}},
{{0x00000001, 0}, Leaf{0x000906C0, 0x00800800, 0x4FF8EBBF, 0xBFEBFBFF}},
});
const auto info = GetX86Info();
EXPECT_STREQ(info.vendor, "GenuineIntel");
EXPECT_EQ(info.family, 0x06);
EXPECT_EQ(info.model, 0x9C);
EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_ATOM_TMT);
}
// https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel0090661_ElkhartLake_CPUID01.txt
TEST_F(CpuidX86Test, INTEL_ATOM_TMT_ELKHART_LAKE) {
cpu().SetLeaves({
{{0x00000000, 0}, Leaf{0x0000001B, 0x756E6547, 0x6C65746E, 0x49656E69}},
{{0x00000001, 0}, Leaf{0x00090661, 0x00800800, 0x4FF8EBBF, 0xBFEBFBFF}},
});
const auto info = GetX86Info();
EXPECT_STREQ(info.vendor, "GenuineIntel");
EXPECT_EQ(info.family, 0x06);
EXPECT_EQ(info.model, 0x96);
EXPECT_EQ(GetX86Microarchitecture(&info), X86Microarchitecture::INTEL_ATOM_TMT);
}
// http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00306F2_HaswellEP2_CPUID.txt // http://users.atw.hu/instlatx64/GenuineIntel/GenuineIntel00306F2_HaswellEP2_CPUID.txt
TEST_F(CpuidX86Test, INTEL_HASWELL_LZCNT) { TEST_F(CpuidX86Test, INTEL_HASWELL_LZCNT) {
cpu().SetLeaves({ cpu().SetLeaves({