From 75ec988188f62281efe7bf1d133338751369bb4c Mon Sep 17 00:00:00 2001
From: michael-roe <2479665+michael-roe@users.noreply.github.com>
Date: Mon, 24 Apr 2023 14:36:22 +0100
Subject: [PATCH] Add RISCV vector extension (#289)

Co-authored-by: Michael Roe <michael-roe@users.noreply.github.com>
---
 include/cpuinfo_riscv.h    |  2 ++
 include/internal/hwcaps.h  |  1 +
 src/impl_riscv_linux.c     |  1 +
 test/cpuinfo_riscv_test.cc | 24 ++++++++++++++++++++++++
 4 files changed, 28 insertions(+)

diff --git a/include/cpuinfo_riscv.h b/include/cpuinfo_riscv.h
index a51477f..1fa7aa5 100644
--- a/include/cpuinfo_riscv.h
+++ b/include/cpuinfo_riscv.h
@@ -36,6 +36,7 @@ typedef struct {
   int D : 1;         // Standard Extension for Double-Precision Floating-Point
   int Q : 1;         // Standard Extension for Quad-Precision Floating-Point
   int C : 1;         // Standard Extension for Compressed Instructions
+  int V : 1;         // Standard Extension for Vector Instructions
   int Zicsr : 1;     // Control and Status Register (CSR)
   int Zifencei : 1;  // Instruction-Fetch Fence
 } RiscvFeatures;
@@ -55,6 +56,7 @@ typedef enum {
   RISCV_D,
   RISCV_Q,
   RISCV_C,
+  RISCV_V,
   RISCV_Zicsr,
   RISCV_Zifencei,
   RISCV_LAST_,
diff --git a/include/internal/hwcaps.h b/include/internal/hwcaps.h
index 5ce349b..3290cc9 100644
--- a/include/internal/hwcaps.h
+++ b/include/internal/hwcaps.h
@@ -214,6 +214,7 @@ CPU_FEATURES_START_CPP_NAMESPACE
 #define RISCV_HWCAP_D (1UL << ('D' - 'A'))
 #define RISCV_HWCAP_Q (1UL << ('Q' - 'A'))
 #define RISCV_HWCAP_C (1UL << ('C' - 'A'))
+#define RISCV_HWCAP_V (1UL << ('V' - 'A'))
 
 typedef struct {
   unsigned long hwcaps;
diff --git a/src/impl_riscv_linux.c b/src/impl_riscv_linux.c
index 1a7fcef..8abec6e 100644
--- a/src/impl_riscv_linux.c
+++ b/src/impl_riscv_linux.c
@@ -39,6 +39,7 @@
   LINE(RISCV_D, D, "d", RISCV_HWCAP_D, 0)              \
   LINE(RISCV_Q, Q, "q", RISCV_HWCAP_Q, 0)              \
   LINE(RISCV_C, C, "c", RISCV_HWCAP_C, 0)              \
+  LINE(RISCV_V, V, "v", RISCV_HWCAP_V, 0)              \
   LINE(RISCV_Zicsr, Zicsr, "_zicsr", 0, 0)             \
   LINE(RISCV_Zifencei, Zifencei, "_zifencei", 0, 0)
 #define INTROSPECTION_PREFIX Riscv
diff --git a/test/cpuinfo_riscv_test.cc b/test/cpuinfo_riscv_test.cc
index 92f637e..2ffe2b3 100644
--- a/test/cpuinfo_riscv_test.cc
+++ b/test/cpuinfo_riscv_test.cc
@@ -41,6 +41,7 @@ uarch : thead,c906)");
   EXPECT_TRUE(info.features.D);
   EXPECT_FALSE(info.features.Q);
   EXPECT_TRUE(info.features.C);
+  EXPECT_FALSE(info.features.V);
 }
 
 // https://github.com/ThomasKaiser/sbc-bench/blob/284e82b016ec1beeac42a5fcbe556b670f68441a/results/Kendryte-K510-4.17.0.cpuinfo
@@ -67,6 +68,7 @@ mmu	: sv39");
   EXPECT_TRUE(info.features.D);
   EXPECT_FALSE(info.features.Q);
   EXPECT_TRUE(info.features.C);
+  EXPECT_FALSE(info.features.V);
 }
 
 // https://github.com/ThomasKaiser/sbc-bench/blob/284e82b016ec1beeac42a5fcbe556b670f68441a/results/T-Head-C910-5.10.4.cpuinfo
@@ -109,6 +111,7 @@ cpu-vector	: 0.7.1");
   EXPECT_TRUE(info.features.D);
   EXPECT_FALSE(info.features.Q);
   EXPECT_TRUE(info.features.C);
+  EXPECT_FALSE(info.features.V);
 }
 
 TEST(CpuinfoRiscvTest, UnknownFromCpuInfo) {
@@ -150,6 +153,27 @@ uarch     : sifive,bullet0)");
   EXPECT_TRUE(info.features.D);
   EXPECT_FALSE(info.features.Q);
   EXPECT_TRUE(info.features.C);
+  EXPECT_FALSE(info.features.V);
+}
+
+TEST(CpuinfoRiscvTest, QemuCpuInfo) {
+  ResetHwcaps();
+  auto& fs = GetEmptyFilesystem();
+  fs.CreateFile("/proc/cpuinfo", R"(
+processor	: 0
+hart		: 0
+isa		: rv64imafdcvh_zba_zbb_zbc_zbs
+mmu		: sv48)");
+  const auto info = GetRiscvInfo();
+  EXPECT_FALSE(info.features.RV32I);
+  EXPECT_TRUE(info.features.RV64I);
+  EXPECT_TRUE(info.features.M);
+  EXPECT_TRUE(info.features.A);
+  EXPECT_TRUE(info.features.F);
+  EXPECT_TRUE(info.features.D);
+  EXPECT_FALSE(info.features.Q);
+  EXPECT_TRUE(info.features.C);
+  EXPECT_TRUE(info.features.V);
 }
 
 }  // namespace