From 319bd6f26be9232cc534e376f1d1ce50505394c2 Mon Sep 17 00:00:00 2001
From: fuzun <fuzun54@outlook.com>
Date: Thu, 30 Aug 2018 06:11:35 +0300
Subject: [PATCH 1/8] Change feature variables to unsigned int to fully comply
 with 'true' and 'false' & IsBitSet()

It seems that ' : 1' alignments cause signed integers to be either -1 or 0. While -1 is true and 0 is false reverse might not be always correct when true is defined 1.

Maybe change feature variables to bool ?
---
 include/cpuinfo_aarch64.h | 14 +++----
 include/cpuinfo_arm.h     | 26 ++++++-------
 include/cpuinfo_mips.h    |  4 +-
 include/cpuinfo_ppc.h     | 82 +++++++++++++++++++--------------------
 include/cpuinfo_x86.h     | 60 ++++++++++++++--------------
 5 files changed, 93 insertions(+), 93 deletions(-)

diff --git a/include/cpuinfo_aarch64.h b/include/cpuinfo_aarch64.h
index b8826ed..b9c2844 100644
--- a/include/cpuinfo_aarch64.h
+++ b/include/cpuinfo_aarch64.h
@@ -20,13 +20,13 @@
 CPU_FEATURES_START_CPP_NAMESPACE
 
 typedef struct {
-  int fp : 1;     // Floating-point.
-  int asimd : 1;  // Advanced SIMD.
-  int aes : 1;    // Hardware-accelerated Advanced Encryption Standard.
-  int pmull : 1;  // Polynomial multiply long.
-  int sha1 : 1;   // Hardware-accelerated SHA1.
-  int sha2 : 1;   // Hardware-accelerated SHA2-256.
-  int crc32 : 1;  // Hardware-accelerated CRC-32.
+  unsigned int fp : 1;     // Floating-point.
+  unsigned int asimd : 1;  // Advanced SIMD.
+  unsigned int aes : 1;    // Hardware-accelerated Advanced Encryption Standard.
+  unsigned int pmull : 1;  // Polynomial multiply long.
+  unsigned int sha1 : 1;   // Hardware-accelerated SHA1.
+  unsigned int sha2 : 1;   // Hardware-accelerated SHA2-256.
+  unsigned int crc32 : 1;  // Hardware-accelerated CRC-32.
 
   // Make sure to update Aarch64FeaturesEnum below if you add a field here.
 } Aarch64Features;
diff --git a/include/cpuinfo_arm.h b/include/cpuinfo_arm.h
index 7a94bb0..ca08381 100644
--- a/include/cpuinfo_arm.h
+++ b/include/cpuinfo_arm.h
@@ -20,19 +20,19 @@
 CPU_FEATURES_START_CPP_NAMESPACE
 
 typedef struct {
-  int vfp : 1;       // Vector Floating Point.
-  int iwmmxt : 1;    // Intel Wireless MMX Technology.
-  int neon : 1;      // Advanced SIMD.
-  int vfpv3 : 1;     // VFP version 3
-  int vfpv3d16 : 1;  // VFP version 3 with 16 D-registers
-  int vfpv4 : 1;     // VFP version 4 with fast context switching
-  int idiva : 1;     // SDIV and UDIV hardware division in ARM mode.
-  int idivt : 1;     // SDIV and UDIV hardware division in Thumb mode.
-  int aes : 1;       // Hardware-accelerated Advanced Encryption Standard.
-  int pmull : 1;     // Polynomial multiply long.
-  int sha1 : 1;      // Hardware-accelerated SHA1.
-  int sha2 : 1;      // Hardware-accelerated SHA2-256.
-  int crc32 : 1;     // Hardware-accelerated CRC-32.
+  unsigned int vfp : 1;       // Vector Floating Point.
+  unsigned int iwmmxt : 1;    // Intel Wireless MMX Technology.
+  unsigned int neon : 1;      // Advanced SIMD.
+  unsigned int vfpv3 : 1;     // VFP version 3
+  unsigned int vfpv3d16 : 1;  // VFP version 3 with 16 D-registers
+  unsigned int vfpv4 : 1;     // VFP version 4 with fast context switching
+  unsigned int idiva : 1;     // SDIV and UDIV hardware division in ARM mode.
+  unsigned int idivt : 1;     // SDIV and UDIV hardware division in Thumb mode.
+  unsigned int aes : 1;       // Hardware-accelerated Advanced Encryption Standard.
+  unsigned int pmull : 1;     // Polynomial multiply long.
+  unsigned int sha1 : 1;      // Hardware-accelerated SHA1.
+  unsigned int sha2 : 1;      // Hardware-accelerated SHA2-256.
+  unsigned int crc32 : 1;     // Hardware-accelerated CRC-32.
 
   // Make sure to update ArmFeaturesEnum below if you add a field here.
 } ArmFeatures;
diff --git a/include/cpuinfo_mips.h b/include/cpuinfo_mips.h
index 48c23a1..dd31fab 100644
--- a/include/cpuinfo_mips.h
+++ b/include/cpuinfo_mips.h
@@ -20,9 +20,9 @@
 CPU_FEATURES_START_CPP_NAMESPACE
 
 typedef struct {
-  int msa : 1;  // MIPS SIMD Architecture
+  unsigned int msa : 1;  // MIPS SIMD Architecture
                 // https://www.mips.com/products/architectures/ase/simd/
-  int eva : 1;  // Enhanced Virtual Addressing
+  unsigned int eva : 1;  // Enhanced Virtual Addressing
                 // https://www.mips.com/products/architectures/mips64/
 
   // Make sure to update MipsFeaturesEnum below if you add a field here.
diff --git a/include/cpuinfo_ppc.h b/include/cpuinfo_ppc.h
index 654155d..7aa8bc3 100644
--- a/include/cpuinfo_ppc.h
+++ b/include/cpuinfo_ppc.h
@@ -21,47 +21,47 @@
 CPU_FEATURES_START_CPP_NAMESPACE
 
 typedef struct {
-  int ppc32 : 1;
-  int ppc64 : 1;
-  int ppc601 : 1;
-  int altivec : 1;
-  int fpu : 1;
-  int mmu : 1;
-  int mac_4xx : 1;
-  int unifiedcache : 1;
-  int spe : 1;
-  int efpsingle : 1;
-  int efpdouble : 1;
-  int no_tb : 1;
-  int power4 : 1;
-  int power5 : 1;
-  int power5plus : 1;
-  int cell : 1;
-  int booke : 1;
-  int smt : 1;
-  int icachesnoop : 1;
-  int arch205 : 1;
-  int pa6t : 1;
-  int dfp : 1;
-  int power6ext : 1;
-  int arch206 : 1;
-  int vsx : 1;
-  int pseries_perfmon_compat : 1;
-  int truele : 1;
-  int ppcle : 1;
-  int arch207 : 1;
-  int htm : 1;
-  int dscr : 1;
-  int ebb : 1;
-  int isel : 1;
-  int tar : 1;
-  int vcrypto : 1;
-  int htm_nosc : 1;
-  int arch300 : 1;
-  int ieee128 : 1;
-  int darn : 1;
-  int scv : 1;
-  int htm_no_suspend : 1;
+  unsigned int ppc32 : 1;
+  unsigned int ppc64 : 1;
+  unsigned int ppc601 : 1;
+  unsigned int altivec : 1;
+  unsigned int fpu : 1;
+  unsigned int mmu : 1;
+  unsigned int mac_4xx : 1;
+  unsigned int unifiedcache : 1;
+  unsigned int spe : 1;
+  unsigned int efpsingle : 1;
+  unsigned int efpdouble : 1;
+  unsigned int no_tb : 1;
+  unsigned int power4 : 1;
+  unsigned int power5 : 1;
+  unsigned int power5plus : 1;
+  unsigned int cell : 1;
+  unsigned int booke : 1;
+  unsigned int smt : 1;
+  unsigned int icachesnoop : 1;
+  unsigned int arch205 : 1;
+  unsigned int pa6t : 1;
+  unsigned int dfp : 1;
+  unsigned int power6ext : 1;
+  unsigned int arch206 : 1;
+  unsigned int vsx : 1;
+  unsigned int pseries_perfmon_compat : 1;
+  unsigned int truele : 1;
+  unsigned int ppcle : 1;
+  unsigned int arch207 : 1;
+  unsigned int htm : 1;
+  unsigned int dscr : 1;
+  unsigned int ebb : 1;
+  unsigned int isel : 1;
+  unsigned int tar : 1;
+  unsigned int vcrypto : 1;
+  unsigned int htm_nosc : 1;
+  unsigned int arch300 : 1;
+  unsigned int ieee128 : 1;
+  unsigned int darn : 1;
+  unsigned int scv : 1;
+  unsigned int htm_no_suspend : 1;
 
   // Make sure to update PPCFeaturesEnum below if you add a field here.
 } PPCFeatures;
diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h
index 0123ddb..521d253 100644
--- a/include/cpuinfo_x86.h
+++ b/include/cpuinfo_x86.h
@@ -21,40 +21,40 @@ CPU_FEATURES_START_CPP_NAMESPACE
 
 // See https://en.wikipedia.org/wiki/CPUID for a list of x86 cpu features.
 typedef struct {
-  int aes : 1;
-  int erms : 1;
-  int f16c : 1;
-  int fma3 : 1;
-  int vpclmulqdq : 1;
-  int bmi1 : 1;
-  int bmi2 : 1;
+  unsigned int aes : 1;
+  unsigned int erms : 1;
+  unsigned int f16c : 1;
+  unsigned int fma3 : 1;
+  unsigned int vpclmulqdq : 1;
+  unsigned int bmi1 : 1;
+  unsigned int bmi2 : 1;
 
-  int ssse3 : 1;
-  int sse4_1 : 1;
-  int sse4_2 : 1;
+  unsigned int ssse3 : 1;
+  unsigned int sse4_1 : 1;
+  unsigned int sse4_2 : 1;
 
-  int avx : 1;
-  int avx2 : 1;
+  unsigned int avx : 1;
+  unsigned int avx2 : 1;
 
-  int avx512f : 1;
-  int avx512cd : 1;
-  int avx512er : 1;
-  int avx512pf : 1;
-  int avx512bw : 1;
-  int avx512dq : 1;
-  int avx512vl : 1;
-  int avx512ifma : 1;
-  int avx512vbmi : 1;
-  int avx512vbmi2 : 1;
-  int avx512vnni : 1;
-  int avx512bitalg : 1;
-  int avx512vpopcntdq : 1;
-  int avx512_4vnniw : 1;
-  int avx512_4vbmi2 : 1;
+  unsigned int avx512f : 1;
+  unsigned int avx512cd : 1;
+  unsigned int avx512er : 1;
+  unsigned int avx512pf : 1;
+  unsigned int avx512bw : 1;
+  unsigned int avx512dq : 1;
+  unsigned int avx512vl : 1;
+  unsigned int avx512ifma : 1;
+  unsigned int avx512vbmi : 1;
+  unsigned int avx512vbmi2 : 1;
+  unsigned int avx512vnni : 1;
+  unsigned int avx512bitalg : 1;
+  unsigned int avx512vpopcntdq : 1;
+  unsigned int avx512_4vnniw : 1;
+  unsigned int avx512_4vbmi2 : 1;
 
-  int smx : 1;
-  int sgx : 1;
-  int cx16 : 1;  // aka. CMPXCHG16B
+  unsigned int smx : 1;
+  unsigned int sgx : 1;
+  unsigned int cx16 : 1;  // aka. CMPXCHG16B
 
   // Make sure to update X86FeaturesEnum below if you add a field here.
 } X86Features;

From 9d9134cf0bfd026d3239f49d7c9112f227f77e82 Mon Sep 17 00:00:00 2001
From: fuzun <fuzun54@outlook.com>
Date: Thu, 30 Aug 2018 06:13:02 +0300
Subject: [PATCH 2/8] Parantheses added to CPUID macro

---
 src/cpuinfo_x86.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/cpuinfo_x86.c b/src/cpuinfo_x86.c
index 390e8c9..0114817 100644
--- a/src/cpuinfo_x86.c
+++ b/src/cpuinfo_x86.c
@@ -149,7 +149,7 @@ X86Info GetX86Info(void) {
   return info;
 }
 
-#define CPUID(FAMILY, MODEL) (((FAMILY & 0xFF) << 8) | (MODEL & 0xFF))
+#define CPUID(FAMILY, MODEL) ((((FAMILY) & 0xFF) << 8) | ((MODEL) & 0xFF))
 
 X86Microarchitecture GetX86Microarchitecture(const X86Info* info) {
   if (memcmp(info->vendor, "GenuineIntel", sizeof(info->vendor)) == 0) {

From 68462fb78ff1febef90a3683b8ee0b65eaec8d9b Mon Sep 17 00:00:00 2001
From: fuzun <fuzun54@outlook.com>
Date: Thu, 30 Aug 2018 06:22:54 +0300
Subject: [PATCH 3/8] Suppress analysis warning

---
 include/internal/bit_utils.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/internal/bit_utils.h b/include/internal/bit_utils.h
index 75f0cdd..bc965cb 100644
--- a/include/internal/bit_utils.h
+++ b/include/internal/bit_utils.h
@@ -28,7 +28,7 @@ inline static bool IsBitSet(uint32_t reg, uint32_t bit) {
 
 inline static uint32_t ExtractBitRange(uint32_t reg, uint32_t msb,
                                        uint32_t lsb) {
-  const uint64_t bits = msb - lsb + 1;
+  const uint64_t bits = msb - lsb + 1ULL;
   const uint64_t mask = (1ULL << bits) - 1ULL;
   assert(msb >= lsb);
   return (reg >> lsb) & mask;

From f189298f4f89a7f29e9bec2f35b8d3b2aa5cadcd Mon Sep 17 00:00:00 2001
From: fuzun <fuzun54@outlook.com>
Date: Sat, 8 Sep 2018 05:16:00 +0300
Subject: [PATCH 4/8] Revert "Change feature variables to unsigned int to fully
 comply with 'true' and 'false' & IsBitSet()"

This reverts commit 319bd6f26be9232cc534e376f1d1ce50505394c2.
---
 include/cpuinfo_aarch64.h | 14 +++----
 include/cpuinfo_arm.h     | 26 ++++++-------
 include/cpuinfo_mips.h    |  4 +-
 include/cpuinfo_ppc.h     | 82 +++++++++++++++++++--------------------
 include/cpuinfo_x86.h     | 60 ++++++++++++++--------------
 5 files changed, 93 insertions(+), 93 deletions(-)

diff --git a/include/cpuinfo_aarch64.h b/include/cpuinfo_aarch64.h
index b9c2844..b8826ed 100644
--- a/include/cpuinfo_aarch64.h
+++ b/include/cpuinfo_aarch64.h
@@ -20,13 +20,13 @@
 CPU_FEATURES_START_CPP_NAMESPACE
 
 typedef struct {
-  unsigned int fp : 1;     // Floating-point.
-  unsigned int asimd : 1;  // Advanced SIMD.
-  unsigned int aes : 1;    // Hardware-accelerated Advanced Encryption Standard.
-  unsigned int pmull : 1;  // Polynomial multiply long.
-  unsigned int sha1 : 1;   // Hardware-accelerated SHA1.
-  unsigned int sha2 : 1;   // Hardware-accelerated SHA2-256.
-  unsigned int crc32 : 1;  // Hardware-accelerated CRC-32.
+  int fp : 1;     // Floating-point.
+  int asimd : 1;  // Advanced SIMD.
+  int aes : 1;    // Hardware-accelerated Advanced Encryption Standard.
+  int pmull : 1;  // Polynomial multiply long.
+  int sha1 : 1;   // Hardware-accelerated SHA1.
+  int sha2 : 1;   // Hardware-accelerated SHA2-256.
+  int crc32 : 1;  // Hardware-accelerated CRC-32.
 
   // Make sure to update Aarch64FeaturesEnum below if you add a field here.
 } Aarch64Features;
diff --git a/include/cpuinfo_arm.h b/include/cpuinfo_arm.h
index ca08381..7a94bb0 100644
--- a/include/cpuinfo_arm.h
+++ b/include/cpuinfo_arm.h
@@ -20,19 +20,19 @@
 CPU_FEATURES_START_CPP_NAMESPACE
 
 typedef struct {
-  unsigned int vfp : 1;       // Vector Floating Point.
-  unsigned int iwmmxt : 1;    // Intel Wireless MMX Technology.
-  unsigned int neon : 1;      // Advanced SIMD.
-  unsigned int vfpv3 : 1;     // VFP version 3
-  unsigned int vfpv3d16 : 1;  // VFP version 3 with 16 D-registers
-  unsigned int vfpv4 : 1;     // VFP version 4 with fast context switching
-  unsigned int idiva : 1;     // SDIV and UDIV hardware division in ARM mode.
-  unsigned int idivt : 1;     // SDIV and UDIV hardware division in Thumb mode.
-  unsigned int aes : 1;       // Hardware-accelerated Advanced Encryption Standard.
-  unsigned int pmull : 1;     // Polynomial multiply long.
-  unsigned int sha1 : 1;      // Hardware-accelerated SHA1.
-  unsigned int sha2 : 1;      // Hardware-accelerated SHA2-256.
-  unsigned int crc32 : 1;     // Hardware-accelerated CRC-32.
+  int vfp : 1;       // Vector Floating Point.
+  int iwmmxt : 1;    // Intel Wireless MMX Technology.
+  int neon : 1;      // Advanced SIMD.
+  int vfpv3 : 1;     // VFP version 3
+  int vfpv3d16 : 1;  // VFP version 3 with 16 D-registers
+  int vfpv4 : 1;     // VFP version 4 with fast context switching
+  int idiva : 1;     // SDIV and UDIV hardware division in ARM mode.
+  int idivt : 1;     // SDIV and UDIV hardware division in Thumb mode.
+  int aes : 1;       // Hardware-accelerated Advanced Encryption Standard.
+  int pmull : 1;     // Polynomial multiply long.
+  int sha1 : 1;      // Hardware-accelerated SHA1.
+  int sha2 : 1;      // Hardware-accelerated SHA2-256.
+  int crc32 : 1;     // Hardware-accelerated CRC-32.
 
   // Make sure to update ArmFeaturesEnum below if you add a field here.
 } ArmFeatures;
diff --git a/include/cpuinfo_mips.h b/include/cpuinfo_mips.h
index dd31fab..48c23a1 100644
--- a/include/cpuinfo_mips.h
+++ b/include/cpuinfo_mips.h
@@ -20,9 +20,9 @@
 CPU_FEATURES_START_CPP_NAMESPACE
 
 typedef struct {
-  unsigned int msa : 1;  // MIPS SIMD Architecture
+  int msa : 1;  // MIPS SIMD Architecture
                 // https://www.mips.com/products/architectures/ase/simd/
-  unsigned int eva : 1;  // Enhanced Virtual Addressing
+  int eva : 1;  // Enhanced Virtual Addressing
                 // https://www.mips.com/products/architectures/mips64/
 
   // Make sure to update MipsFeaturesEnum below if you add a field here.
diff --git a/include/cpuinfo_ppc.h b/include/cpuinfo_ppc.h
index 7aa8bc3..654155d 100644
--- a/include/cpuinfo_ppc.h
+++ b/include/cpuinfo_ppc.h
@@ -21,47 +21,47 @@
 CPU_FEATURES_START_CPP_NAMESPACE
 
 typedef struct {
-  unsigned int ppc32 : 1;
-  unsigned int ppc64 : 1;
-  unsigned int ppc601 : 1;
-  unsigned int altivec : 1;
-  unsigned int fpu : 1;
-  unsigned int mmu : 1;
-  unsigned int mac_4xx : 1;
-  unsigned int unifiedcache : 1;
-  unsigned int spe : 1;
-  unsigned int efpsingle : 1;
-  unsigned int efpdouble : 1;
-  unsigned int no_tb : 1;
-  unsigned int power4 : 1;
-  unsigned int power5 : 1;
-  unsigned int power5plus : 1;
-  unsigned int cell : 1;
-  unsigned int booke : 1;
-  unsigned int smt : 1;
-  unsigned int icachesnoop : 1;
-  unsigned int arch205 : 1;
-  unsigned int pa6t : 1;
-  unsigned int dfp : 1;
-  unsigned int power6ext : 1;
-  unsigned int arch206 : 1;
-  unsigned int vsx : 1;
-  unsigned int pseries_perfmon_compat : 1;
-  unsigned int truele : 1;
-  unsigned int ppcle : 1;
-  unsigned int arch207 : 1;
-  unsigned int htm : 1;
-  unsigned int dscr : 1;
-  unsigned int ebb : 1;
-  unsigned int isel : 1;
-  unsigned int tar : 1;
-  unsigned int vcrypto : 1;
-  unsigned int htm_nosc : 1;
-  unsigned int arch300 : 1;
-  unsigned int ieee128 : 1;
-  unsigned int darn : 1;
-  unsigned int scv : 1;
-  unsigned int htm_no_suspend : 1;
+  int ppc32 : 1;
+  int ppc64 : 1;
+  int ppc601 : 1;
+  int altivec : 1;
+  int fpu : 1;
+  int mmu : 1;
+  int mac_4xx : 1;
+  int unifiedcache : 1;
+  int spe : 1;
+  int efpsingle : 1;
+  int efpdouble : 1;
+  int no_tb : 1;
+  int power4 : 1;
+  int power5 : 1;
+  int power5plus : 1;
+  int cell : 1;
+  int booke : 1;
+  int smt : 1;
+  int icachesnoop : 1;
+  int arch205 : 1;
+  int pa6t : 1;
+  int dfp : 1;
+  int power6ext : 1;
+  int arch206 : 1;
+  int vsx : 1;
+  int pseries_perfmon_compat : 1;
+  int truele : 1;
+  int ppcle : 1;
+  int arch207 : 1;
+  int htm : 1;
+  int dscr : 1;
+  int ebb : 1;
+  int isel : 1;
+  int tar : 1;
+  int vcrypto : 1;
+  int htm_nosc : 1;
+  int arch300 : 1;
+  int ieee128 : 1;
+  int darn : 1;
+  int scv : 1;
+  int htm_no_suspend : 1;
 
   // Make sure to update PPCFeaturesEnum below if you add a field here.
 } PPCFeatures;
diff --git a/include/cpuinfo_x86.h b/include/cpuinfo_x86.h
index 521d253..0123ddb 100644
--- a/include/cpuinfo_x86.h
+++ b/include/cpuinfo_x86.h
@@ -21,40 +21,40 @@ CPU_FEATURES_START_CPP_NAMESPACE
 
 // See https://en.wikipedia.org/wiki/CPUID for a list of x86 cpu features.
 typedef struct {
-  unsigned int aes : 1;
-  unsigned int erms : 1;
-  unsigned int f16c : 1;
-  unsigned int fma3 : 1;
-  unsigned int vpclmulqdq : 1;
-  unsigned int bmi1 : 1;
-  unsigned int bmi2 : 1;
+  int aes : 1;
+  int erms : 1;
+  int f16c : 1;
+  int fma3 : 1;
+  int vpclmulqdq : 1;
+  int bmi1 : 1;
+  int bmi2 : 1;
 
-  unsigned int ssse3 : 1;
-  unsigned int sse4_1 : 1;
-  unsigned int sse4_2 : 1;
+  int ssse3 : 1;
+  int sse4_1 : 1;
+  int sse4_2 : 1;
 
-  unsigned int avx : 1;
-  unsigned int avx2 : 1;
+  int avx : 1;
+  int avx2 : 1;
 
-  unsigned int avx512f : 1;
-  unsigned int avx512cd : 1;
-  unsigned int avx512er : 1;
-  unsigned int avx512pf : 1;
-  unsigned int avx512bw : 1;
-  unsigned int avx512dq : 1;
-  unsigned int avx512vl : 1;
-  unsigned int avx512ifma : 1;
-  unsigned int avx512vbmi : 1;
-  unsigned int avx512vbmi2 : 1;
-  unsigned int avx512vnni : 1;
-  unsigned int avx512bitalg : 1;
-  unsigned int avx512vpopcntdq : 1;
-  unsigned int avx512_4vnniw : 1;
-  unsigned int avx512_4vbmi2 : 1;
+  int avx512f : 1;
+  int avx512cd : 1;
+  int avx512er : 1;
+  int avx512pf : 1;
+  int avx512bw : 1;
+  int avx512dq : 1;
+  int avx512vl : 1;
+  int avx512ifma : 1;
+  int avx512vbmi : 1;
+  int avx512vbmi2 : 1;
+  int avx512vnni : 1;
+  int avx512bitalg : 1;
+  int avx512vpopcntdq : 1;
+  int avx512_4vnniw : 1;
+  int avx512_4vbmi2 : 1;
 
-  unsigned int smx : 1;
-  unsigned int sgx : 1;
-  unsigned int cx16 : 1;  // aka. CMPXCHG16B
+  int smx : 1;
+  int sgx : 1;
+  int cx16 : 1;  // aka. CMPXCHG16B
 
   // Make sure to update X86FeaturesEnum below if you add a field here.
 } X86Features;

From 58a232c560cbd5d341aeb67b890cbe263528a755 Mon Sep 17 00:00:00 2001
From: fuzun <fuzun54@outlook.com>
Date: Sat, 8 Sep 2018 05:56:35 +0300
Subject: [PATCH 5/8] Different approach for -1 & true compliance

---
 include/internal/bit_utils.h |  7 +++++--
 src/cpuinfo_arm.c            | 13 +++++++------
 2 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/include/internal/bit_utils.h b/include/internal/bit_utils.h
index bc965cb..a889cd6 100644
--- a/include/internal/bit_utils.h
+++ b/include/internal/bit_utils.h
@@ -22,8 +22,11 @@
 
 CPU_FEATURES_START_CPP_NAMESPACE
 
-inline static bool IsBitSet(uint32_t reg, uint32_t bit) {
-  return (reg >> bit) & 0x1;
+#define TRUE -1
+// #define FALSE 0
+
+inline static int IsBitSet(uint32_t reg, uint32_t bit) {
+  return ((reg >> bit) & 0x1) ? TRUE : false;
 }
 
 inline static uint32_t ExtractBitRange(uint32_t reg, uint32_t msb,
diff --git a/src/cpuinfo_arm.c b/src/cpuinfo_arm.c
index 3ea0641..6c1813f 100644
--- a/src/cpuinfo_arm.c
+++ b/src/cpuinfo_arm.c
@@ -127,7 +127,7 @@ static void FixErrors(ArmInfo* const info,
       // slightly updated.
       if (info->architecture >= 7 &&
           proc_cpu_info_data->hardware_reports_goldfish) {
-        info->features.idiva = true;
+        info->features.idiva = TRUE;
       }
       break;
     case 0x511004D0:
@@ -138,15 +138,16 @@ static void FixErrors(ArmInfo* const info,
     case 0x510006F3:
       // The Nexus 4 (Qualcomm Krait) kernel configuration forgets to report
       // IDIV support.
-      info->features.idiva = true;
-      info->features.idivt = true;
+      info->features.idiva = TRUE;
+      info->features.idivt = TRUE;
       break;
   }
 
+
   // Propagate cpu features.
-  if (info->features.vfpv4) info->features.vfpv3 = true;
-  if (info->features.neon) info->features.vfpv3 = true;
-  if (info->features.vfpv3) info->features.vfp = true;
+  if (info->features.vfpv4) info->features.vfpv3 = TRUE;
+  if (info->features.neon) info->features.vfpv3 = TRUE;
+  if (info->features.vfpv3) info->features.vfp = TRUE;
 }
 
 static void FillProcCpuInfoData(ArmInfo* const info,

From 78223d1be73c551ec75603166260841296ab41e2 Mon Sep 17 00:00:00 2001
From: fuzun <fuzun54@outlook.com>
Date: Sat, 8 Sep 2018 06:12:07 +0300
Subject: [PATCH 6/8] Cast added for macros in test for new IsBitSet

---
 test/bit_utils_test.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/test/bit_utils_test.cc b/test/bit_utils_test.cc
index 8937cbc..2e5c812 100644
--- a/test/bit_utils_test.cc
+++ b/test/bit_utils_test.cc
@@ -23,18 +23,18 @@ TEST(UtilsTest, IsBitSet) {
   for (size_t bit_set = 0; bit_set < 32; ++bit_set) {
     const uint32_t value = 1UL << bit_set;
     for (size_t i = 0; i < 32; ++i) {
-      EXPECT_EQ(IsBitSet(value, i), i == bit_set);
+      EXPECT_EQ((bool)IsBitSet(value, i), i == bit_set);
     }
   }
 
   // testing 0, all bits should be 0.
   for (size_t i = 0; i < 32; ++i) {
-    EXPECT_FALSE(IsBitSet(0, i));
+    EXPECT_FALSE((bool)IsBitSet(0, i));
   }
 
   // testing ~0, all bits should be 1.
   for (size_t i = 0; i < 32; ++i) {
-    EXPECT_TRUE(IsBitSet(-1, i));
+    EXPECT_TRUE((bool)IsBitSet(-1, i));
   }
 }
 

From f6c8a5d92d349165aeb32a58dc4cad1b758d9aee Mon Sep 17 00:00:00 2001
From: fuzun <fuzun54@outlook.com>
Date: Tue, 11 Sep 2018 17:24:35 +0300
Subject: [PATCH 7/8] Revert "Different approach for -1 & true compliance"

This reverts commit 58a232c560cbd5d341aeb67b890cbe263528a755.
---
 include/internal/bit_utils.h |  7 ++-----
 src/cpuinfo_arm.c            | 13 ++++++-------
 2 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/include/internal/bit_utils.h b/include/internal/bit_utils.h
index a889cd6..bc965cb 100644
--- a/include/internal/bit_utils.h
+++ b/include/internal/bit_utils.h
@@ -22,11 +22,8 @@
 
 CPU_FEATURES_START_CPP_NAMESPACE
 
-#define TRUE -1
-// #define FALSE 0
-
-inline static int IsBitSet(uint32_t reg, uint32_t bit) {
-  return ((reg >> bit) & 0x1) ? TRUE : false;
+inline static bool IsBitSet(uint32_t reg, uint32_t bit) {
+  return (reg >> bit) & 0x1;
 }
 
 inline static uint32_t ExtractBitRange(uint32_t reg, uint32_t msb,
diff --git a/src/cpuinfo_arm.c b/src/cpuinfo_arm.c
index 6c1813f..3ea0641 100644
--- a/src/cpuinfo_arm.c
+++ b/src/cpuinfo_arm.c
@@ -127,7 +127,7 @@ static void FixErrors(ArmInfo* const info,
       // slightly updated.
       if (info->architecture >= 7 &&
           proc_cpu_info_data->hardware_reports_goldfish) {
-        info->features.idiva = TRUE;
+        info->features.idiva = true;
       }
       break;
     case 0x511004D0:
@@ -138,16 +138,15 @@ static void FixErrors(ArmInfo* const info,
     case 0x510006F3:
       // The Nexus 4 (Qualcomm Krait) kernel configuration forgets to report
       // IDIV support.
-      info->features.idiva = TRUE;
-      info->features.idivt = TRUE;
+      info->features.idiva = true;
+      info->features.idivt = true;
       break;
   }
 
-
   // Propagate cpu features.
-  if (info->features.vfpv4) info->features.vfpv3 = TRUE;
-  if (info->features.neon) info->features.vfpv3 = TRUE;
-  if (info->features.vfpv3) info->features.vfp = TRUE;
+  if (info->features.vfpv4) info->features.vfpv3 = true;
+  if (info->features.neon) info->features.vfpv3 = true;
+  if (info->features.vfpv3) info->features.vfp = true;
 }
 
 static void FillProcCpuInfoData(ArmInfo* const info,

From 954eb4cc580690db3e6d7897f782a9ef312d3a12 Mon Sep 17 00:00:00 2001
From: fuzun <fuzun54@outlook.com>
Date: Tue, 11 Sep 2018 17:43:40 +0300
Subject: [PATCH 8/8] Revert "Cast added for macros in test for new IsBitSet"

This reverts commit 78223d1be73c551ec75603166260841296ab41e2.
---
 test/bit_utils_test.cc | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/test/bit_utils_test.cc b/test/bit_utils_test.cc
index 2e5c812..8937cbc 100644
--- a/test/bit_utils_test.cc
+++ b/test/bit_utils_test.cc
@@ -23,18 +23,18 @@ TEST(UtilsTest, IsBitSet) {
   for (size_t bit_set = 0; bit_set < 32; ++bit_set) {
     const uint32_t value = 1UL << bit_set;
     for (size_t i = 0; i < 32; ++i) {
-      EXPECT_EQ((bool)IsBitSet(value, i), i == bit_set);
+      EXPECT_EQ(IsBitSet(value, i), i == bit_set);
     }
   }
 
   // testing 0, all bits should be 0.
   for (size_t i = 0; i < 32; ++i) {
-    EXPECT_FALSE((bool)IsBitSet(0, i));
+    EXPECT_FALSE(IsBitSet(0, i));
   }
 
   // testing ~0, all bits should be 1.
   for (size_t i = 0; i < 32; ++i) {
-    EXPECT_TRUE((bool)IsBitSet(-1, i));
+    EXPECT_TRUE(IsBitSet(-1, i));
   }
 }