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mirror of https://github.com/google/cpu_features.git synced 2025-07-01 13:21:13 +02:00

[NFC] clang-format the code base

This commit is contained in:
Guillaume Chatelet
2023-09-25 07:35:53 +00:00
parent ec7d390a90
commit 8cfb520efb
11 changed files with 101 additions and 97 deletions

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@ -26,7 +26,7 @@ CPU_FEATURES_START_CPP_NAMESPACE
typedef struct {
// Base
int CPUCFG : 1; // Instruction for Identify CPU Features
int CPUCFG : 1; // Instruction for Identify CPU Features
// Extension
int LAM : 1; // Extension for Atomic Memory Access Instructions
@ -36,7 +36,8 @@ typedef struct {
int LASX : 1; // Extension for Loongson Advanced SIMD eXtension
int CRC32 : 1; // Extension for Cyclic Redundancy Check Instructions
int COMPLEX : 1; // Extension for Complex Vector Operation Instructions
int CRYPTO : 1; // Extension for Encryption And Decryption Vector Instructions
int CRYPTO : 1; // Extension for Encryption And Decryption Vector
// Instructions
int LVZ : 1; // Extension for Virtualization
int LBT_X86 : 1; // Extension for X86 Binary Translation Extension
int LBT_ARM : 1; // Extension for ARM Binary Translation Extension
@ -69,7 +70,7 @@ typedef enum {
LoongArchInfo GetLoongArchInfo(void);
int GetLoongArchFeaturesEnumValue(const LoongArchFeatures* features,
LoongArchFeaturesEnum value);
LoongArchFeaturesEnum value);
const char* GetLoongArchFeaturesEnumName(LoongArchFeaturesEnum);
CPU_FEATURES_END_CPP_NAMESPACE

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@ -21,20 +21,20 @@
CPU_FEATURES_START_CPP_NAMESPACE
typedef struct {
int msa : 1; // MIPS SIMD Architecture
// https://www.mips.com/products/architectures/ase/simd/
int eva : 1; // Enhanced Virtual Addressing
// https://www.mips.com/products/architectures/mips64/
int r6 : 1; // True if is release 6 of the processor.
int mips16 : 1; // Compressed instructions
int mdmx : 1; // MIPS Digital Media Extension
int mips3d : 1; // 3D graphics acceleration
// MIPS(r) Architecture for Programmers, Volume IV-c
int smart : 1; // Smart-card cryptography
// MIPS(r) Architecture for Programmers, Volume IV-d
int dsp : 1; // Digital Signal Processing
// MIPS(r) Architecture for Programmers, Volume IV-e
// https://www.mips.com/products/architectures/ase/dsp/
int msa : 1; // MIPS SIMD Architecture
// https://www.mips.com/products/architectures/ase/simd/
int eva : 1; // Enhanced Virtual Addressing
// https://www.mips.com/products/architectures/mips64/
int r6 : 1; // True if is release 6 of the processor.
int mips16 : 1; // Compressed instructions
int mdmx : 1; // MIPS Digital Media Extension
int mips3d : 1; // 3D graphics acceleration
// MIPS(r) Architecture for Programmers, Volume IV-c
int smart : 1; // Smart-card cryptography
// MIPS(r) Architecture for Programmers, Volume IV-d
int dsp : 1; // Digital Signal Processing
// MIPS(r) Architecture for Programmers, Volume IV-e
// https://www.mips.com/products/architectures/ase/dsp/
// Make sure to update MipsFeaturesEnum below if you add a field here.
} MipsFeatures;

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@ -21,29 +21,29 @@
CPU_FEATURES_START_CPP_NAMESPACE
typedef struct {
int esan3: 1; // instructions named N3, "backported" to esa-mode
int zarch: 1; // z/Architecture mode active
int stfle: 1; // store-facility-list-extended
int msa: 1; // message-security assist
int ldisp: 1; // long-displacement
int eimm: 1; // extended-immediate
int dfp: 1; // decimal floating point & perform floating point operation
int edat: 1; // huge page support
int etf3eh: 1; // extended-translation facility 3 enhancement
int highgprs: 1; // 64-bit register support for 31-bit processes
int te: 1; // transactional execution
int vx: 1; // vector extension facility
int vxd: 1; // vector-packed-decimal facility
int vxe: 1; // vector-enhancement facility 1
int gs: 1; // guarded-storage facility
int vxe2: 1; // vector-enhancements facility 2
int vxp: 1; // vector-packed-decimal-enhancement facility
int sort: 1; // enhanced-sort facility
int dflt: 1; // deflate-conversion facility
int vxp2: 1; // vector-packed-decimal-enhancement facility 2
int nnpa: 1; // neural network processing assist facility
int pcimio: 1; // PCI mio facility
int sie: 1; // virtualization support
int esan3 : 1; // instructions named N3, "backported" to esa-mode
int zarch : 1; // z/Architecture mode active
int stfle : 1; // store-facility-list-extended
int msa : 1; // message-security assist
int ldisp : 1; // long-displacement
int eimm : 1; // extended-immediate
int dfp : 1; // decimal floating point & perform floating point operation
int edat : 1; // huge page support
int etf3eh : 1; // extended-translation facility 3 enhancement
int highgprs : 1; // 64-bit register support for 31-bit processes
int te : 1; // transactional execution
int vx : 1; // vector extension facility
int vxd : 1; // vector-packed-decimal facility
int vxe : 1; // vector-enhancement facility 1
int gs : 1; // guarded-storage facility
int vxe2 : 1; // vector-enhancements facility 2
int vxp : 1; // vector-packed-decimal-enhancement facility
int sort : 1; // enhanced-sort facility
int dflt : 1; // deflate-conversion facility
int vxp2 : 1; // vector-packed-decimal-enhancement facility 2
int nnpa : 1; // neural network processing assist facility
int pcimio : 1; // PCI mio facility
int sie : 1; // virtualization support
// Make sure to update S390XFeaturesEnum below if you add a field here.
} S390XFeatures;
@ -55,11 +55,11 @@ typedef struct {
S390XInfo GetS390XInfo(void);
typedef struct {
char platform[64]; // 0 terminated string
char platform[64]; // 0 terminated string
} S390XPlatformTypeStrings;
typedef struct {
int num_processors; // -1 if N/A
int num_processors; // -1 if N/A
S390XPlatformTypeStrings type;
} S390XPlatformStrings;
@ -95,7 +95,8 @@ typedef enum {
S390X_LAST_,
} S390XFeaturesEnum;
int GetS390XFeaturesEnumValue(const S390XFeatures* features, S390XFeaturesEnum value);
int GetS390XFeaturesEnumValue(const S390XFeatures* features,
S390XFeaturesEnum value);
const char* GetS390XFeaturesEnumName(S390XFeaturesEnum);

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@ -109,8 +109,8 @@ typedef struct {
int fs_rep_stosb : 1; // Fast short REP STOSB
int fs_rep_cmpsb_scasb : 1; // Fast short REP CMPSB/SCASB
int lam: 1; // Intel Linear Address Mask
int uai: 1; // AMD Upper Address Ignore
int lam : 1; // Intel Linear Address Mask
int uai : 1; // AMD Upper Address Ignore
// Make sure to update X86FeaturesEnum below if you add a field here.
} X86Features;