diff --git a/include/cpuinfo_aarch64.h b/include/cpuinfo_aarch64.h index d124b5f..18a3313 100644 --- a/include/cpuinfo_aarch64.h +++ b/include/cpuinfo_aarch64.h @@ -169,6 +169,27 @@ typedef struct { int ecv : 1; // Enhanced counter virtualization. int afp : 1; // Alternate floating-point behaviour. int rpres : 1; // 12-bit reciprocal (square root) estimate precision. + int mte3 : 1; // MTE asymmetric fault handling. + int sme : 1; // Scalable Matrix Extension. + int smei16i64 : 1; // 16-bit to 64-bit integer widening outer product. + int smef64f64 : 1; // FP64 to FP64 outer product. + int smei8i32 : 1; // 8-bit to 32-bit integer widening outer product. + int smef16f32 : 1; // FP16 to FP32 outer product. + int smeb16f32 : 1; // BFloat16 to FP32 outper product. + int smef32f32 : 1; // FP32 to FP32 outer product. + int smefa64 : 1; // Full A64 support for SME in streaming mode. + int wfxt : 1; // WFE and WFI with timeout. + int ebf16 : 1; // Extended BFloat16 instructions. + int sveebf16 : 1; // SVE BFloat16 instructions. + int cssc : 1; // Common short sequence compression instructions. + int rprfm : 1; // Range Prefetch Memory hint instruction. + int sve2p1 : 1; // Scalable Vector Extension (version 2.1). + int sme2 : 1; // Scalable Matrix Extension (version 2). + int sme2p1 : 1; // Scalable Matrix Extension (version 2.1). + int smei16i32 : 1; // 16-bit to 64-bit integer widening outer product. + int smebi32i32 : 1; // 1-bit binary to 32-bit integer outer product. + int smeb16b16 : 1; // SME2.1 BFloat16 instructions. + int smef16f16 : 1; // FP16 to FP16 outer product. // Make sure to update Aarch64FeaturesEnum below if you add a field here. } Aarch64Features; @@ -242,6 +263,27 @@ typedef enum { AARCH64_ECV, AARCH64_AFP, AARCH64_RPRES, + AARCH64_MTE3, + AARCH64_SME, + AARCH64_SME_I16I64, + AARCH64_SME_F64F64, + AARCH64_SME_I8I32, + AARCH64_SME_F16F32, + AARCH64_SME_B16F32, + AARCH64_SME_F32F32, + AARCH64_SME_FA64, + AARCH64_WFXT, + AARCH64_EBF16, + AARCH64_SVE_EBF16, + AARCH64_CSSC, + AARCH64_RPRFM, + AARCH64_SVE2P1, + AARCH64_SME2, + AARCH64_SME2P1, + AARCH64_SME_I16I32, + AARCH64_SME_BI32I32, + AARCH64_SME_B16B16, + AARCH64_SME_F16F16, AARCH64_LAST_, } Aarch64FeaturesEnum; diff --git a/include/internal/hwcaps.h b/include/internal/hwcaps.h index 3290cc9..e532979 100644 --- a/include/internal/hwcaps.h +++ b/include/internal/hwcaps.h @@ -83,6 +83,27 @@ CPU_FEATURES_START_CPP_NAMESPACE #define AARCH64_HWCAP2_ECV (1UL << 19) #define AARCH64_HWCAP2_AFP (1UL << 20) #define AARCH64_HWCAP2_RPRES (1UL << 21) +#define AARCH64_HWCAP2_MTE3 (1UL << 22) +#define AARCH64_HWCAP2_SME (1UL << 23) +#define AARCH64_HWCAP2_SME_I16I64 (1UL << 24) +#define AARCH64_HWCAP2_SME_F64F64 (1UL << 25) +#define AARCH64_HWCAP2_SME_I8I32 (1UL << 26) +#define AARCH64_HWCAP2_SME_F16F32 (1UL << 27) +#define AARCH64_HWCAP2_SME_B16F32 (1UL << 28) +#define AARCH64_HWCAP2_SME_F32F32 (1UL << 29) +#define AARCH64_HWCAP2_SME_FA64 (1UL << 30) +#define AARCH64_HWCAP2_WFXT (1UL << 31) +#define AARCH64_HWCAP2_EBF16 (1UL << 32) +#define AARCH64_HWCAP2_SVE_EBF16 (1UL << 33) +#define AARCH64_HWCAP2_CSSC (1UL << 34) +#define AARCH64_HWCAP2_RPRFM (1UL << 35) +#define AARCH64_HWCAP2_SVE2P1 (1UL << 36) +#define AARCH64_HWCAP2_SME2 (1UL << 37) +#define AARCH64_HWCAP2_SME2P1 (1UL << 38) +#define AARCH64_HWCAP2_SME_I16I32 (1UL << 39) +#define AARCH64_HWCAP2_SME_BI32I32 (1UL << 40) +#define AARCH64_HWCAP2_SME_B16B16 (1UL << 41) +#define AARCH64_HWCAP2_SME_F16F16 (1UL << 42) // http://elixir.free-electrons.com/linux/latest/source/arch/arm/include/uapi/asm/hwcap.h #define ARM_HWCAP_SWP (1UL << 0) diff --git a/src/impl_aarch64_linux_or_android.c b/src/impl_aarch64_linux_or_android.c index ef923d9..f06a52f 100644 --- a/src/impl_aarch64_linux_or_android.c +++ b/src/impl_aarch64_linux_or_android.c @@ -22,62 +22,91 @@ //////////////////////////////////////////////////////////////////////////////// // Definitions for introspection. //////////////////////////////////////////////////////////////////////////////// -#define INTROSPECTION_TABLE \ - LINE(AARCH64_FP, fp, "fp", AARCH64_HWCAP_FP, 0) \ - LINE(AARCH64_ASIMD, asimd, "asimd", AARCH64_HWCAP_ASIMD, 0) \ - LINE(AARCH64_EVTSTRM, evtstrm, "evtstrm", AARCH64_HWCAP_EVTSTRM, 0) \ - LINE(AARCH64_AES, aes, "aes", AARCH64_HWCAP_AES, 0) \ - LINE(AARCH64_PMULL, pmull, "pmull", AARCH64_HWCAP_PMULL, 0) \ - LINE(AARCH64_SHA1, sha1, "sha1", AARCH64_HWCAP_SHA1, 0) \ - LINE(AARCH64_SHA2, sha2, "sha2", AARCH64_HWCAP_SHA2, 0) \ - LINE(AARCH64_CRC32, crc32, "crc32", AARCH64_HWCAP_CRC32, 0) \ - LINE(AARCH64_ATOMICS, atomics, "atomics", AARCH64_HWCAP_ATOMICS, 0) \ - LINE(AARCH64_FPHP, fphp, "fphp", AARCH64_HWCAP_FPHP, 0) \ - LINE(AARCH64_ASIMDHP, asimdhp, "asimdhp", AARCH64_HWCAP_ASIMDHP, 0) \ - LINE(AARCH64_CPUID, cpuid, "cpuid", AARCH64_HWCAP_CPUID, 0) \ - LINE(AARCH64_ASIMDRDM, asimdrdm, "asimdrdm", AARCH64_HWCAP_ASIMDRDM, 0) \ - LINE(AARCH64_JSCVT, jscvt, "jscvt", AARCH64_HWCAP_JSCVT, 0) \ - LINE(AARCH64_FCMA, fcma, "fcma", AARCH64_HWCAP_FCMA, 0) \ - LINE(AARCH64_LRCPC, lrcpc, "lrcpc", AARCH64_HWCAP_LRCPC, 0) \ - LINE(AARCH64_DCPOP, dcpop, "dcpop", AARCH64_HWCAP_DCPOP, 0) \ - LINE(AARCH64_SHA3, sha3, "sha3", AARCH64_HWCAP_SHA3, 0) \ - LINE(AARCH64_SM3, sm3, "sm3", AARCH64_HWCAP_SM3, 0) \ - LINE(AARCH64_SM4, sm4, "sm4", AARCH64_HWCAP_SM4, 0) \ - LINE(AARCH64_ASIMDDP, asimddp, "asimddp", AARCH64_HWCAP_ASIMDDP, 0) \ - LINE(AARCH64_SHA512, sha512, "sha512", AARCH64_HWCAP_SHA512, 0) \ - LINE(AARCH64_SVE, sve, "sve", AARCH64_HWCAP_SVE, 0) \ - LINE(AARCH64_ASIMDFHM, asimdfhm, "asimdfhm", AARCH64_HWCAP_ASIMDFHM, 0) \ - LINE(AARCH64_DIT, dit, "dit", AARCH64_HWCAP_DIT, 0) \ - LINE(AARCH64_USCAT, uscat, "uscat", AARCH64_HWCAP_USCAT, 0) \ - LINE(AARCH64_ILRCPC, ilrcpc, "ilrcpc", AARCH64_HWCAP_ILRCPC, 0) \ - LINE(AARCH64_FLAGM, flagm, "flagm", AARCH64_HWCAP_FLAGM, 0) \ - LINE(AARCH64_SSBS, ssbs, "ssbs", AARCH64_HWCAP_SSBS, 0) \ - LINE(AARCH64_SB, sb, "sb", AARCH64_HWCAP_SB, 0) \ - LINE(AARCH64_PACA, paca, "paca", AARCH64_HWCAP_PACA, 0) \ - LINE(AARCH64_PACG, pacg, "pacg", AARCH64_HWCAP_PACG, 0) \ - LINE(AARCH64_DCPODP, dcpodp, "dcpodp", 0, AARCH64_HWCAP2_DCPODP) \ - LINE(AARCH64_SVE2, sve2, "sve2", 0, AARCH64_HWCAP2_SVE2) \ - LINE(AARCH64_SVEAES, sveaes, "sveaes", 0, AARCH64_HWCAP2_SVEAES) \ - LINE(AARCH64_SVEPMULL, svepmull, "svepmull", 0, AARCH64_HWCAP2_SVEPMULL) \ - LINE(AARCH64_SVEBITPERM, svebitperm, "svebitperm", 0, \ - AARCH64_HWCAP2_SVEBITPERM) \ - LINE(AARCH64_SVESHA3, svesha3, "svesha3", 0, AARCH64_HWCAP2_SVESHA3) \ - LINE(AARCH64_SVESM4, svesm4, "svesm4", 0, AARCH64_HWCAP2_SVESM4) \ - LINE(AARCH64_FLAGM2, flagm2, "flagm2", 0, AARCH64_HWCAP2_FLAGM2) \ - LINE(AARCH64_FRINT, frint, "frint", 0, AARCH64_HWCAP2_FRINT) \ - LINE(AARCH64_SVEI8MM, svei8mm, "svei8mm", 0, AARCH64_HWCAP2_SVEI8MM) \ - LINE(AARCH64_SVEF32MM, svef32mm, "svef32mm", 0, AARCH64_HWCAP2_SVEF32MM) \ - LINE(AARCH64_SVEF64MM, svef64mm, "svef64mm", 0, AARCH64_HWCAP2_SVEF64MM) \ - LINE(AARCH64_SVEBF16, svebf16, "svebf16", 0, AARCH64_HWCAP2_SVEBF16) \ - LINE(AARCH64_I8MM, i8mm, "i8mm", 0, AARCH64_HWCAP2_I8MM) \ - LINE(AARCH64_BF16, bf16, "bf16", 0, AARCH64_HWCAP2_BF16) \ - LINE(AARCH64_DGH, dgh, "dgh", 0, AARCH64_HWCAP2_DGH) \ - LINE(AARCH64_RNG, rng, "rng", 0, AARCH64_HWCAP2_RNG) \ - LINE(AARCH64_BTI, bti, "bti", 0, AARCH64_HWCAP2_BTI) \ - LINE(AARCH64_MTE, mte, "mte", 0, AARCH64_HWCAP2_MTE) \ - LINE(AARCH64_ECV, ecv, "ecv", 0, AARCH64_HWCAP2_ECV) \ - LINE(AARCH64_AFP, afp, "afp", 0, AARCH64_HWCAP2_AFP) \ - LINE(AARCH64_RPRES, rpres, "rpres", 0, AARCH64_HWCAP2_RPRES) +#define INTROSPECTION_TABLE \ + LINE(AARCH64_FP, fp, "fp", AARCH64_HWCAP_FP, 0) \ + LINE(AARCH64_ASIMD, asimd, "asimd", AARCH64_HWCAP_ASIMD, 0) \ + LINE(AARCH64_EVTSTRM, evtstrm, "evtstrm", AARCH64_HWCAP_EVTSTRM, 0) \ + LINE(AARCH64_AES, aes, "aes", AARCH64_HWCAP_AES, 0) \ + LINE(AARCH64_PMULL, pmull, "pmull", AARCH64_HWCAP_PMULL, 0) \ + LINE(AARCH64_SHA1, sha1, "sha1", AARCH64_HWCAP_SHA1, 0) \ + LINE(AARCH64_SHA2, sha2, "sha2", AARCH64_HWCAP_SHA2, 0) \ + LINE(AARCH64_CRC32, crc32, "crc32", AARCH64_HWCAP_CRC32, 0) \ + LINE(AARCH64_ATOMICS, atomics, "atomics", AARCH64_HWCAP_ATOMICS, 0) \ + LINE(AARCH64_FPHP, fphp, "fphp", AARCH64_HWCAP_FPHP, 0) \ + LINE(AARCH64_ASIMDHP, asimdhp, "asimdhp", AARCH64_HWCAP_ASIMDHP, 0) \ + LINE(AARCH64_CPUID, cpuid, "cpuid", AARCH64_HWCAP_CPUID, 0) \ + LINE(AARCH64_ASIMDRDM, asimdrdm, "asimdrdm", AARCH64_HWCAP_ASIMDRDM, 0) \ + LINE(AARCH64_JSCVT, jscvt, "jscvt", AARCH64_HWCAP_JSCVT, 0) \ + LINE(AARCH64_FCMA, fcma, "fcma", AARCH64_HWCAP_FCMA, 0) \ + LINE(AARCH64_LRCPC, lrcpc, "lrcpc", AARCH64_HWCAP_LRCPC, 0) \ + LINE(AARCH64_DCPOP, dcpop, "dcpop", AARCH64_HWCAP_DCPOP, 0) \ + LINE(AARCH64_SHA3, sha3, "sha3", AARCH64_HWCAP_SHA3, 0) \ + LINE(AARCH64_SM3, sm3, "sm3", AARCH64_HWCAP_SM3, 0) \ + LINE(AARCH64_SM4, sm4, "sm4", AARCH64_HWCAP_SM4, 0) \ + LINE(AARCH64_ASIMDDP, asimddp, "asimddp", AARCH64_HWCAP_ASIMDDP, 0) \ + LINE(AARCH64_SHA512, sha512, "sha512", AARCH64_HWCAP_SHA512, 0) \ + LINE(AARCH64_SVE, sve, "sve", AARCH64_HWCAP_SVE, 0) \ + LINE(AARCH64_ASIMDFHM, asimdfhm, "asimdfhm", AARCH64_HWCAP_ASIMDFHM, 0) \ + LINE(AARCH64_DIT, dit, "dit", AARCH64_HWCAP_DIT, 0) \ + LINE(AARCH64_USCAT, uscat, "uscat", AARCH64_HWCAP_USCAT, 0) \ + LINE(AARCH64_ILRCPC, ilrcpc, "ilrcpc", AARCH64_HWCAP_ILRCPC, 0) \ + LINE(AARCH64_FLAGM, flagm, "flagm", AARCH64_HWCAP_FLAGM, 0) \ + LINE(AARCH64_SSBS, ssbs, "ssbs", AARCH64_HWCAP_SSBS, 0) \ + LINE(AARCH64_SB, sb, "sb", AARCH64_HWCAP_SB, 0) \ + LINE(AARCH64_PACA, paca, "paca", AARCH64_HWCAP_PACA, 0) \ + LINE(AARCH64_PACG, pacg, "pacg", AARCH64_HWCAP_PACG, 0) \ + LINE(AARCH64_DCPODP, dcpodp, "dcpodp", 0, AARCH64_HWCAP2_DCPODP) \ + LINE(AARCH64_SVE2, sve2, "sve2", 0, AARCH64_HWCAP2_SVE2) \ + LINE(AARCH64_SVEAES, sveaes, "sveaes", 0, AARCH64_HWCAP2_SVEAES) \ + LINE(AARCH64_SVEPMULL, svepmull, "svepmull", 0, AARCH64_HWCAP2_SVEPMULL) \ + LINE(AARCH64_SVEBITPERM, svebitperm, "svebitperm", 0, \ + AARCH64_HWCAP2_SVEBITPERM) \ + LINE(AARCH64_SVESHA3, svesha3, "svesha3", 0, AARCH64_HWCAP2_SVESHA3) \ + LINE(AARCH64_SVESM4, svesm4, "svesm4", 0, AARCH64_HWCAP2_SVESM4) \ + LINE(AARCH64_FLAGM2, flagm2, "flagm2", 0, AARCH64_HWCAP2_FLAGM2) \ + LINE(AARCH64_FRINT, frint, "frint", 0, AARCH64_HWCAP2_FRINT) \ + LINE(AARCH64_SVEI8MM, svei8mm, "svei8mm", 0, AARCH64_HWCAP2_SVEI8MM) \ + LINE(AARCH64_SVEF32MM, svef32mm, "svef32mm", 0, AARCH64_HWCAP2_SVEF32MM) \ + LINE(AARCH64_SVEF64MM, svef64mm, "svef64mm", 0, AARCH64_HWCAP2_SVEF64MM) \ + LINE(AARCH64_SVEBF16, svebf16, "svebf16", 0, AARCH64_HWCAP2_SVEBF16) \ + LINE(AARCH64_I8MM, i8mm, "i8mm", 0, AARCH64_HWCAP2_I8MM) \ + LINE(AARCH64_BF16, bf16, "bf16", 0, AARCH64_HWCAP2_BF16) \ + LINE(AARCH64_DGH, dgh, "dgh", 0, AARCH64_HWCAP2_DGH) \ + LINE(AARCH64_RNG, rng, "rng", 0, AARCH64_HWCAP2_RNG) \ + LINE(AARCH64_BTI, bti, "bti", 0, AARCH64_HWCAP2_BTI) \ + LINE(AARCH64_MTE, mte, "mte", 0, AARCH64_HWCAP2_MTE) \ + LINE(AARCH64_ECV, ecv, "ecv", 0, AARCH64_HWCAP2_ECV) \ + LINE(AARCH64_AFP, afp, "afp", 0, AARCH64_HWCAP2_AFP) \ + LINE(AARCH64_RPRES, rpres, "rpres", 0, AARCH64_HWCAP2_RPRES) \ + LINE(AARCH64_MTE3, mte3, "mte3", 0, AARCH64_HWCAP2_MTE3) \ + LINE(AARCH64_SME, sme, "sme", 0, AARCH64_HWCAP2_SME) \ + LINE(AARCH64_SME_I16I64, smei16i64, "smei16i64", 0, \ + AARCH64_HWCAP2_SME_I16I64) \ + LINE(AARCH64_SME_F64F64, smef64f64, "smef64f64", 0, \ + AARCH64_HWCAP2_SME_F64F64) \ + LINE(AARCH64_SME_I8I32, smei8i32, "smei8i32", 0, AARCH64_HWCAP2_SME_I8I32) \ + LINE(AARCH64_SME_F16F32, smef16f32, "smef16f32", 0, \ + AARCH64_HWCAP2_SME_F16F32) \ + LINE(AARCH64_SME_B16F32, smeb16f32, "smeb16f32", 0, \ + AARCH64_HWCAP2_SME_B16F32) \ + LINE(AARCH64_SME_F32F32, smef32f32, "smef32f32", 0, \ + AARCH64_HWCAP2_SME_F32F32) \ + LINE(AARCH64_SME_FA64, smefa64, "smefa64", 0, AARCH64_HWCAP2_SME_FA64) \ + LINE(AARCH64_WFXT, wfxt, "wfxt", 0, AARCH64_HWCAP2_WFXT) \ + LINE(AARCH64_EBF16, ebf16, "ebf16", 0, AARCH64_HWCAP2_EBF16) \ + LINE(AARCH64_SVE_EBF16, sveebf16, "sveebf16", 0, AARCH64_HWCAP2_SVE_EBF16) \ + LINE(AARCH64_CSSC, cssc, "cssc", 0, AARCH64_HWCAP2_CSSC) \ + LINE(AARCH64_RPRFM, rprfm, "rprfm", 0, AARCH64_HWCAP2_RPRFM) \ + LINE(AARCH64_SVE2P1, sve2p1, "sve2p1", 0, AARCH64_HWCAP2_SVE2P1) \ + LINE(AARCH64_SME2, sme2, "sme2", 0, AARCH64_HWCAP2_SME2) \ + LINE(AARCH64_SME2P1, sme2p1, "sme2p1", 0, AARCH64_HWCAP2_SME2P1) \ + LINE(AARCH64_SME_I16I32, smei16i32, "smei16i32", 0, \ + AARCH64_HWCAP2_SME_I16I32) \ + LINE(AARCH64_SME_BI32I32, smebi32i32, "smebi32i32", 0, \ + AARCH64_HWCAP2_SME_BI32I32) \ + LINE(AARCH64_SME_B16B16, smeb16b16, "smeb16b16", 0, \ + AARCH64_HWCAP2_SME_B16B16) \ + LINE(AARCH64_SME_F16F16, smef16f16, "smef16f16", 0, AARCH64_HWCAP2_SME_F16F16) #define INTROSPECTION_PREFIX Aarch64 #define INTROSPECTION_ENUM_PREFIX AARCH64 #include "define_introspection_and_hwcaps.inl" diff --git a/test/cpuinfo_aarch64_test.cc b/test/cpuinfo_aarch64_test.cc index ef9abae..e32367a 100644 --- a/test/cpuinfo_aarch64_test.cc +++ b/test/cpuinfo_aarch64_test.cc @@ -244,6 +244,27 @@ CPU revision : 3)"); EXPECT_FALSE(info.features.ecv); EXPECT_FALSE(info.features.afp); EXPECT_FALSE(info.features.rpres); + EXPECT_FALSE(info.features.mte3); + EXPECT_FALSE(info.features.sme); + EXPECT_FALSE(info.features.smei16i64); + EXPECT_FALSE(info.features.smef64f64); + EXPECT_FALSE(info.features.smei8i32); + EXPECT_FALSE(info.features.smef16f32); + EXPECT_FALSE(info.features.smeb16f32); + EXPECT_FALSE(info.features.smef32f32); + EXPECT_FALSE(info.features.smefa64); + EXPECT_FALSE(info.features.wfxt); + EXPECT_FALSE(info.features.ebf16); + EXPECT_FALSE(info.features.sveebf16); + EXPECT_FALSE(info.features.cssc); + EXPECT_FALSE(info.features.rprfm); + EXPECT_FALSE(info.features.sve2p1); + EXPECT_FALSE(info.features.sme2); + EXPECT_FALSE(info.features.sme2p1); + EXPECT_FALSE(info.features.smei16i32); + EXPECT_FALSE(info.features.smebi32i32); + EXPECT_FALSE(info.features.smeb16b16); + EXPECT_FALSE(info.features.smef16f16); } #endif // CPU_FEATURES_OS_LINUX