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https://github.com/google/cpu_features.git
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Completed all missing ARM hwcaps. (#79)
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committed by
Guillaume Chatelet

parent
18342789a1
commit
bfd109b687
@ -21,13 +21,18 @@
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CPU_FEATURES_START_CPP_NAMESPACE
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typedef struct {
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int swp : 1; // SWP instruction (atomic read-modify-write)
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int half : 1; // Half-word loads and stores
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int thumb : 1; // Thumb (16-bit instruction set)
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int _26bit : 1; // "26 Bit" Model (Processor status register folded into program counter)
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int fastmult : 1; // 32x32->64-bit multiplication
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int fpa : 1; // Floating point accelerator
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int vfp : 1; // Vector Floating Point.
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int edsp : 1; // DSP extensions (the 'e' variant of the ARM9 CPUs, and all others above)
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int java : 1; // Jazelle (Java bytecode accelerator)
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int iwmmxt : 1; // Intel Wireless MMX Technology.
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int crunch : 1; // MaverickCrunch coprocessor
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int thumbee : 1; // ThumbEE
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int neon : 1; // Advanced SIMD.
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int vfpv3 : 1; // VFP version 3
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int vfpv3d16 : 1; // VFP version 3 with 16 D-registers
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@ -35,6 +40,9 @@ typedef struct {
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int vfpv4 : 1; // VFP version 4 with fast context switching
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int idiva : 1; // SDIV and UDIV hardware division in ARM mode.
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int idivt : 1; // SDIV and UDIV hardware division in Thumb mode.
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int vfpd32 : 1; // VFP with 32 D-registers
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int lpae : 1; // Large Physical Address Extension (>4GB physical memory on 32-bit architecture)
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int evtstrm : 1; // kernel event stream using generic architected timer
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int aes : 1; // Hardware-accelerated Advanced Encryption Standard.
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int pmull : 1; // Polynomial multiply long.
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int sha1 : 1; // Hardware-accelerated SHA1.
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@ -65,13 +73,18 @@ uint32_t GetArmCpuId(const ArmInfo* const info);
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// Introspection functions
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typedef enum {
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ARM_SWP,
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ARM_HALF,
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ARM_THUMB,
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ARM_26BIT,
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ARM_FASTMULT,
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ARM_FPA,
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ARM_VFP,
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ARM_EDSP,
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ARM_JAVA,
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ARM_IWMMXT,
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ARM_CRUNCH,
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ARM_THUMBEE,
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ARM_NEON,
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ARM_VFPV3,
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ARM_VFPV3D16,
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@ -79,6 +92,9 @@ typedef enum {
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ARM_VFPV4,
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ARM_IDIVA,
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ARM_IDIVT,
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ARM_VFPD32,
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ARM_LPAE,
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ARM_EVTSTRM,
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ARM_AES,
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ARM_PMULL,
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ARM_SHA1,
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@ -35,13 +35,18 @@ CPU_FEATURES_START_CPP_NAMESPACE
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#define AARCH64_HWCAP_CRC32 (1UL << 7)
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// http://elixir.free-electrons.com/linux/latest/source/arch/arm/include/uapi/asm/hwcap.h
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#define ARM_HWCAP_SWP (1UL << 0)
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#define ARM_HWCAP_HALF (1UL << 1)
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#define ARM_HWCAP_THUMB (1UL << 2)
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#define ARM_HWCAP_26BIT (1UL << 3)
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#define ARM_HWCAP_FAST_MULT (1UL << 4)
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#define ARM_HWCAP_FPA (1UL << 5)
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#define ARM_HWCAP_VFP (1UL << 6)
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#define ARM_HWCAP_EDSP (1UL << 7)
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#define ARM_HWCAP_JAVA (1UL << 8)
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#define ARM_HWCAP_IWMMXT (1UL << 9)
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#define ARM_HWCAP_CRUNCH (1UL << 10)
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#define ARM_HWCAP_THUMBEE (1UL << 11)
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#define ARM_HWCAP_NEON (1UL << 12)
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#define ARM_HWCAP_VFPV3 (1UL << 13)
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#define ARM_HWCAP_VFPV3D16 (1UL << 14)
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@ -49,6 +54,9 @@ CPU_FEATURES_START_CPP_NAMESPACE
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#define ARM_HWCAP_VFPV4 (1UL << 16)
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#define ARM_HWCAP_IDIVA (1UL << 17)
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#define ARM_HWCAP_IDIVT (1UL << 18)
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#define ARM_HWCAP_VFPD32 (1UL << 19)
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#define ARM_HWCAP_LPAE (1UL << 20)
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#define ARM_HWCAP_EVTSTRM (1UL << 21)
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#define ARM_HWCAP2_AES (1UL << 0)
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#define ARM_HWCAP2_PMULL (1UL << 1)
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#define ARM_HWCAP2_SHA1 (1UL << 2)
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