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24 Commits

Author SHA1 Message Date
Nikolay Hohsadze
0925f6953c
Add cache info for new AMD CPUs (0x8000001D) (#171) 2021-10-18 14:14:29 +02:00
Nikolay Hohsadze
5492c4c561
CPU features for AMD (#165) 2021-06-30 12:38:56 +02:00
Kris Kwiatkowski
d35e2f38eb
Detect Intel's Multi-Precision Add-Carry Instruction Extensions (#157) 2021-05-21 10:47:32 +02:00
natanbc
7ed0b0e50e
Detect Zen 3 (K19) cpus (#152) 
Co-authored-by: natanbc <natanbc@users.noreply.github.com>
 2021-02-25 21:47:39 +01:00
Guillaume Chatelet
3cc8f310d9 [NFC] Update copyright from Google Inc. to Google LLC 2020-10-12 08:55:20 +00:00
Jeff Hammond
17ffb65117
detect AVX-512 FMA count (#125) 
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* second FMA features - incomplete and wrong

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* oops: use T/F not 2/1

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* implement SKX lookup

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

* cleanup AVX512 second FMA code

1) remove debug stuff
2) remove ICX - will add details when available

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* fix CPX detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove elses

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove curly braces from single-line conditional bodies

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* apply clang-format

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

Fixes #120
 2020-09-22 07:29:46 +00:00
Jeff Hammond
33bd72c1bc
detect future Intel AVX/AMX features (#124) 
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AVX512_BF16 and AVX512_VP2INTERSECT detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* correction for KNM features: s/4VBMI2/4FMAPS/g

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AMX/TMUL bits from 319433-040

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fixes #128
 2020-09-21 07:56:26 +00:00
Jeff Hammond
e698327713
add future Intel microarchitectures (#123) 
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fix #127
 2020-09-21 07:54:58 +00:00
gadoofou87
3262a55118 Support x86 FMA4 and SSE4A features 2020-03-12 10:58:41 +00:00
Moxeja
73a121b1ae Differentiate between different Lake uarch 2020-01-06 16:23:29 +01:00
Artem Alekseev
653d581e03 Add support for leaf2 and leaf4 on Intel's x86 arch (#80) 
* Add support for leaf4 on Intel's x86 arch
* Update cpuinfo_x86.h
* Fix typo
* Force compiler to use C99
* Add Intel x86 leaf2 support
* Fixes after review
* Fix review comments
 2019-07-02 16:52:25 +02:00
Artem Alekseev
3ee4a9e801 Support x86 DCA and SS features (#76) 
* Add dca and ss features
* Remove trailing white spaces
 2019-06-19 15:06:05 +02:00
Dr.-Ing. Patrick Siegl
367bc42116 Support x86 features: FPU, TSC, CX8, CLFSH, MMX, VAES, HLE, RTM, RDSEED, CLFLUSHOPT, CLWB, SSE, SSE2, SSE3, PCLMULQDQ (#73) 2019-06-13 11:53:39 +02:00
Guillaume Chatelet
d395dfa026
Add x86 missing feature detections for ndk_compat (#58) 
One more step towards #47.
 2019-01-22 13:19:42 +01:00
Guillaume Chatelet
4155ee7e36
Guarding header use with architecture (#56) 2019-01-18 13:38:22 +01:00
Guillaume Chatelet
9b872ce0b2 Add cx16 (cmpxchg16b) cpuid flag. Fixes #30 2018-03-13 10:58:42 +01:00
Patrik Fiedler
3ee0d62e87
detect intel sgx and smx cpu features for the x86 arch 2018-02-13 11:16:48 +01:00
Guillaume Chatelet
e419573d10 Use CPU_FEATURES_ prefix for namespace macros. 2018-02-12 16:15:15 +01:00
Guillaume Chatelet
11e3e20496 Reverting 338484f6f2176c3d8ede0ed2f3fbd6cf1eb0274c. Fixes #2 2018-02-09 08:55:11 +01:00
Guillaume Chatelet
1d6ba6139c
Merge pull request #5 from bsurmanski/patch-1 
Fix spelling mistake for 'Cannon Lake'
 2018-02-08 16:34:15 +01:00
Guillaume Chatelet
338484f6f2 Fixes #2 - vpclmulqdq should be pclmulqdq. 2018-02-08 11:35:31 +01:00
Brandon Surmanski
efcc49a493
Fix spelling mistake for 'Cannon Lake' 
See:
https://www.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/platform-codenames.html
https://en.wikipedia.org/wiki/Cannon_Lake_(microarchitecture)
 2018-02-07 11:07:00 -08:00
Guillaume Chatelet
8e58ef0d2b Removing THIRD_PARTY_ from C headers. 2018-02-01 10:38:48 +01:00
Guillaume Chatelet
439d371594 Adding code. Closes #0. 2018-02-01 10:03:09 +01:00