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143 Commits

Author SHA1 Message Date
Guillaume Chatelet
ebcdfcaeff Fix missing header 2021-10-29 13:54:41 +00:00
Guillaume Chatelet
f69a25811f make copy and equals inline headers 2021-10-29 12:41:43 +00:00
Guillaume Chatelet
990c55c50f Silence unsused parameters 2021-10-29 10:48:52 +00:00
Guillaume Chatelet
6fd9a8ca58 Make getter/setter static so they don't leak 2021-10-29 10:47:01 +00:00
Guillaume Chatelet
400d4f2836 Fix CpuFeatures_memchr to actually use the provided size argument 2021-10-29 10:10:20 +00:00
Nikolay Hohsadze
5695cc4817 Update uarch detection for Intel processors (#184) 2021-10-29 10:41:50 +02:00
Guillaume Chatelet
deb2a61b80 New code layout - breaking change in cpu_features_macros.h (#194) 
This commit helps with platform code separation (fixes #3). It should also help with the build as we can simply include all `impl_*.c` files regardless of OS / arch.

Note: this patch contains breaking changes in `include/cpu_features_macros.h`
 - `CPU_FEATURES_OS_LINUX_OR_ANDROID` does not exist anymore
 - `CPU_FEATURES_OS_FREEBSD`, `CPU_FEATURES_OS_ANDROID` and `CPU_FEATURES_OS_LINUX` are now mutually exclusive (i.e. `CPU_FEATURES_OS_ANDROID` does not imply `CPU_FEATURES_OS_LINUX`)
 - `CPU_FEATURES_OS_DARWIN` has been renamed into `CPU_FEATURES_OS_MACOS` to be able to target non-Mac Apple products (IOS, TV, WATCH). They are now targetable with `CPU_FEATURES_OS_IPHONE`. This matches Apple naming convention described in [this stackoverflow](https://stackoverflow.com/a/49560690).
 2021-10-28 13:52:46 +02:00
Guillaume Chatelet
c5659bf16f Override CacheInfo only if new data is available via Deterministic Cache Parameters Leaf 
#190
 2021-10-26 15:21:27 +00:00
Guillaume Chatelet
7bd206a75f Fix memory overflow 
Duplicate of #190
 2021-10-26 13:58:42 +00:00
Guillaume Chatelet
769287c384 Fixes #185 (#187) 
Missing `string_view` header and invalid `_Static_assert` statement
 2021-10-25 09:48:46 +02:00
Guillaume Chatelet
cf589a2844 [NFC] Change implementation of FillX86BrandString (#181) 2021-10-21 10:51:00 +02:00
Guillaume Chatelet
32b49eb5e7 Fixes wrong cache detection of old processors (#183) 2021-10-20 17:02:52 +02:00
Nikolay Hohsadze
0925f6953c Add cache info for new AMD CPUs (0x8000001D) (#171) 2021-10-18 14:14:29 +02:00
Guillaume Chatelet
f70dc46cd5 Add separator to CpuFeatures_StringView_HasWord (#174) 2021-10-18 12:52:14 +02:00
Guillaume Chatelet
119943707c Add support for FreeBSD on x86 (#163) 2021-07-02 15:37:03 +02:00
Nikolay Hohsadze
5492c4c561 CPU features for AMD (#165) 2021-06-30 12:38:56 +02:00
Guillaume Chatelet
b3ef4ef49d Avoid leaking internal headers for ppc (#164) 2021-06-30 11:51:26 +02:00
Kris Kwiatkowski
001faefdc3 fix: Return default value from ‘GetCacheTypeString’ (#162) 
The build fails with following message when -Werror
and -Werror=return-type are enabled.

In function ‘GetCacheTypeString’:
	error: control reaches end of non-void function [-Werror=return-type]

Simple fix is to return explicitly communicate to
the compiler that certain block is not reachable.
 2021-06-25 10:28:26 +02:00
Guillaume Chatelet
646b80fa3a [NFC] refactor the code so it's easier to understand the execution flow (#161) 2021-06-23 14:21:05 +00:00
Guillaume Chatelet
108f3d9eca Fix #140 Atom processor detected as X86_UNKNOWN (#160) 2021-06-22 11:12:02 +02:00
Koichi Shiraishi
bc2846e78f Detect AVX512 on Darwin use GetDarwinSysCtlByName("hw.optional.avx512f") (#153) 2021-05-21 11:14:50 +02:00
Kris Kwiatkowski
d35e2f38eb Detect Intel's Multi-Precision Add-Carry Instruction Extensions (#157) 2021-05-21 10:47:32 +02:00
natanbc
7ed0b0e50e Detect Zen 3 (K19) cpus (#152) 
Co-authored-by: natanbc <natanbc@users.noreply.github.com>
 2021-02-25 21:47:39 +01:00
Tamas Zsoldos
e2f6dea65f Update AArch64 features to Linux 5.10 (#149) 
Added feature: MTE.
 2020-12-15 13:28:53 +01:00
Guillaume Chatelet
cdab59af76 [NFC] Simplify build by removing inl files. (#139) 2020-10-13 13:05:04 +02:00
Guillaume Chatelet
9a8f04b24c [NFC] Generate separate tables via macro (#137) 
This is a non functional change, it allows:
 - Getting rid of `unix_features_aggregator`
 - Have a single blob describing the features
 - Fix wrong mocking of `hwcaps`

Downside: abuse of macros makes the code slightly magical and harder to understand.
It think it's still an improvement over the current situation as there's less repetition and less chances to get something wrong.
 2020-10-12 09:50:35 +00:00
Guillaume Chatelet
3cc8f310d9 [NFC] Update copyright from Google Inc. to Google LLC 2020-10-12 08:55:20 +00:00
Tim Gates
c0885fec9b docs: fix simple typo, intented -> intended (#138) 
There is a small typo in src/utils/list_cpu_features.c.

Should read `intended` rather than `intented`.
 2020-10-12 07:20:05 +00:00
Guillaume Chatelet
e63405f118 Remove need for utsname (#136) 2020-10-09 20:40:06 +00:00
Guillaume Chatelet
4795373db2 Fix SSE detection on non-AVX CPUs (#135) 
Fixes #4. This is based on #115 with a few modifications:
 - Removed use of __builtin_cpu_supports since it relies on cpuid and doesn't improve on the current situation,
 - Added detection for all of sse, sse2, sse3, ssse3, sse4_1 and sse4_2,
 - Added tests for Atom, Nehalem, and P3 processors,

Thx to @gadoofou87 for providing the original PR.
It also removes the need for #92

* Fix SSE detection on non-AVX CPUs
* Fixes typo
* Mock OSX sysctlbyname in tests
* Also update other tests
* FakeCpu is reset between each tests
* Fix conflicting name on Windows
* Disable pre AVX cpu sse detection tests on Windows
* Guard OS specific code with macros
* Fix missing import for tests
* Fix wrong function prototype
* Fix wrong mocking of P3 on Windows
* Completely guard OS specific parts in x86 tests
* Store DWORD instead unsigned long for x86 tests
 2020-10-09 15:20:25 +00:00
Guillaume Chatelet
22a5362e11 [NFC] clang-format codebase (#134) 
* [NFC] clang-format codebase

* revert to 80 char columns at the price of uglier table init

* Specifically disabling clang-format for table initialization
 2020-09-23 09:52:20 +00:00
Jeff Hammond
17ffb65117 detect AVX-512 FMA count (#125) 
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* second FMA features - incomplete and wrong

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* oops: use T/F not 2/1

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* implement SKX lookup

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

* cleanup AVX512 second FMA code

1) remove debug stuff
2) remove ICX - will add details when available

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* fix CPX detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove elses

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove curly braces from single-line conditional bodies

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* apply clang-format

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

Fixes #120
 2020-09-22 07:29:46 +00:00
Guillaume Chatelet
76dafc7e3b [NFC] Remove unused max_cpuid_leaf variable (#131) 2020-09-21 14:54:13 +02:00
Jeff Hammond
33bd72c1bc detect future Intel AVX/AMX features (#124) 
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AVX512_BF16 and AVX512_VP2INTERSECT detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* correction for KNM features: s/4VBMI2/4FMAPS/g

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AMX/TMUL bits from 319433-040

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fixes #128
 2020-09-21 07:56:26 +00:00
Jeff Hammond
e698327713 add future Intel microarchitectures (#123) 
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fix #127
 2020-09-21 07:54:58 +00:00
Tamas Zsoldos
73d10ad25b Update features for AArch64 to Linux 5.8 (#122) 
This adds the following features: dcpodp, sve2, sveaes, svepmull,
svebitperm, svesha3, svesm4, flagm2, frint, svei8mm, svef32mm,
svef64mm, svebf16, i8mm, bf16, dgh and rng.

With these, all features used by Linux 5.8 on AArch64 is supported.

Fixes #126
 2020-09-21 07:50:38 +00:00
Corentin Le Molgat
339bfd32be Add OsSupport structure 2020-03-12 10:58:41 +00:00
Corentin Le Molgat
404e462cd4 Move AMD extra flags to its own function 2020-03-12 10:58:41 +00:00
gadoofou87
3262a55118 Support x86 FMA4 and SSE4A features 2020-03-12 10:58:41 +00:00
Guillaume Chatelet
5d55aa1efe Add cache_info data to X86 for list_cpu_features (#105) 
* Add cache_info data to X86 for list_cpu_features
 2020-01-29 15:02:48 +01:00
Guillaume Chatelet
e50d7db3b0 [NFC] Use Designated Initializers 2020-01-29 11:31:10 +01:00
Moxeja
24b8a1de17 Add INTEL_WHL and INTEL_ICL to uarch get name function 2020-01-07 10:18:04 +01:00
Patrick Siegl
3d71a964f5 Use a getter function to avoid manual work for future to-be-added cpu features 2020-01-06 16:24:10 +01:00
Moxeja
73a121b1ae Differentiate between different Lake uarch 2020-01-06 16:23:29 +01:00
Guillaume Chatelet
8a6fd87074 [NFC] Fixed signed shift 
signed shift result (0x80000000) sets the sign bit of the shift expression's type ('int') and becomes negative
 2019-11-13 14:39:06 +01:00
Guillaume Chatelet
99d2363c62 [NFC] fix various errors 2019-11-13 11:22:31 +01:00
Guillaume Chatelet
be306b7b15 [NFC] fix unused and shadowing variables 2019-11-13 11:15:40 +01:00
Guillaume Chatelet
9d2de7fb5c Making sure global variable is aligned without using attributes 2019-11-12 17:12:44 +01:00
Guillaume Chatelet
7298eda2ff Making sure global variable is 8B aligned as well 2019-11-12 16:53:04 +01:00
Guillaume Chatelet
0f2f60ab00 Address comments in https://github.com/google/cpu_features/pull/94 2019-11-12 16:26:00 +01:00