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Commit Graph

106 Commits

Author SHA1 Message Date
3c4801d12d Add AMD ZEN 4 uarch and update detection (#243)
* Add AMD ZEN 4 uarch and update detection

* Add tests via cpuid dump
2022-06-17 11:18:05 +02:00
08f2dc115e Added some MIPS features. (#241)
Co-authored-by: Michael Roe <michael-roe@users.noreply.github.com>
2022-06-01 15:58:29 +02:00
b04a9daf71 Update AArch64 features to Linux 5.17. (#237) 2022-04-27 10:26:29 +02:00
7fe96b1d3d Comply with -Wstrict-prototypes 2022-04-14 11:01:06 +02:00
dedea3a5a7 Comply with -Wstrict-prototypes 2022-04-13 13:21:32 +02:00
40e1c7158d replace sse3 detection with pni when reading /proc/cpuinfo (#225) 2022-02-22 14:19:17 +01:00
1d02169588 Add support for ZHAOXIN CPU (#218) 2022-02-18 16:32:06 +01:00
5f5e6d620f Fix a getauxval comment and expand the Krait idiv workaround (#206)
* Fix getauxval comment (API 18 not 20)

getauxval is available in Android starting with API 18, not 20.

The comment about __ANDROID_API__ appears to have been copied from the
NDK's cpufeatures, which always uses dlopen/dlsym and doesn't assume it
can directly call getauxval, even if __ANDROID_API__ is new enough.
With this project, though, when __ANDROID_API__ is 18 or up, the
CMakeLists.txt file would detect that getauxval is available and define
HAVE_STRONG_GETAUXVAL.

* Broaden Qualcomm Krait idiv workaround

Some Qualcomm Krait CPUs have IDIV support but the kernel doesn't
report it. Previously, this code looked for two CPUs:
 - 0x510006F2 (0x51/'Q', variant 0, part 0x06f, rev 2)
 - 0x510006F3 (0x51/'Q', variant 0, part 0x06f, rev 3)

This check misses my 2013 Nexus 7 device, which has this CPU ID:
 - 0x511006f0 (0x51/'Q', variant 1, part 0x06f, rev 0)

My Nexus 7 device doesn't report idiv through AT_HWCAP or through
/proc/cpuinfo (AT_HWCAP is 0x1b0d7).

Expand the check to anything with:
 - implementer 0x51
 - architecture 7
 - part 0x4d or 0x6f

Part 0x4d appears to be a dual-core Krait (e.g. see
https://crbug.com/341598#c43).

This new matching behavior is a subset of what the upstream kernel
does (patch[1] contributed by CodeAurora), and also closely matches the
behavior of pytorch/cpuinfo.

[1] 120ecfafab
2022-02-01 17:25:05 +01:00
f1801f0ca1 Fix list_cpu_features.exe does not detect SSE42 on Xeon X5650 (Windows) (#220) 2022-01-31 10:15:17 +01:00
149916384b [x86] Embed brand_string and mark FillX86BrandString as deprecated (#214) 2022-01-14 17:20:31 +01:00
aa642e573e [NFC] Avoid polluting global scope 2022-01-14 16:06:30 +00:00
5ed8ef4bbe [NFC][x86] Read all cpuid leaves at once (#213)
This patch reads the most important cpuid leaves and stores the data in
a struct. A followup patch will inline micro architecture detection and
brand string inside X86Info so we don't have to call `ReadLeaves` multiple
times. This wil allow further simplification of `HasSecondFMA` and help
fix https://github.com/google/cpu_features/issues/200.
2022-01-14 14:14:07 +01:00
9d34e6a1c8 Fix #205
Since buffers are a few tens of bytes there is no need for optimized memfunctions. For compile time sizes, the compiler will generate optimal code already.
2021-11-22 16:50:29 +00:00
ebcdfcaeff Fix missing header 2021-10-29 13:54:41 +00:00
f69a25811f make copy and equals inline headers 2021-10-29 12:41:43 +00:00
990c55c50f Silence unsused parameters 2021-10-29 10:48:52 +00:00
6fd9a8ca58 Make getter/setter static so they don't leak 2021-10-29 10:47:01 +00:00
400d4f2836 Fix CpuFeatures_memchr to actually use the provided size argument 2021-10-29 10:10:20 +00:00
5695cc4817 Update uarch detection for Intel processors (#184) 2021-10-29 10:41:50 +02:00
deb2a61b80 New code layout - breaking change in cpu_features_macros.h (#194)
This commit helps with platform code separation (fixes #3). It should also help with the build as we can simply include all `impl_*.c` files regardless of OS / arch.

Note: this patch contains breaking changes in `include/cpu_features_macros.h`
 - `CPU_FEATURES_OS_LINUX_OR_ANDROID` does not exist anymore
 - `CPU_FEATURES_OS_FREEBSD`, `CPU_FEATURES_OS_ANDROID` and `CPU_FEATURES_OS_LINUX` are now mutually exclusive (i.e. `CPU_FEATURES_OS_ANDROID` does not imply `CPU_FEATURES_OS_LINUX`)
 - `CPU_FEATURES_OS_DARWIN` has been renamed into `CPU_FEATURES_OS_MACOS` to be able to target non-Mac Apple products (IOS, TV, WATCH). They are now targetable with `CPU_FEATURES_OS_IPHONE`. This matches Apple naming convention described in [this stackoverflow](https://stackoverflow.com/a/49560690).
2021-10-28 13:52:46 +02:00
c5659bf16f Override CacheInfo only if new data is available via Deterministic Cache Parameters Leaf
#190
2021-10-26 15:21:27 +00:00
7bd206a75f Fix memory overflow
Duplicate of #190
2021-10-26 13:58:42 +00:00
769287c384 Fixes #185 (#187)
Missing `string_view` header and invalid `_Static_assert` statement
2021-10-25 09:48:46 +02:00
cf589a2844 [NFC] Change implementation of FillX86BrandString (#181) 2021-10-21 10:51:00 +02:00
32b49eb5e7 Fixes wrong cache detection of old processors (#183) 2021-10-20 17:02:52 +02:00
0925f6953c Add cache info for new AMD CPUs (0x8000001D) (#171) 2021-10-18 14:14:29 +02:00
f70dc46cd5 Add separator to CpuFeatures_StringView_HasWord (#174) 2021-10-18 12:52:14 +02:00
119943707c Add support for FreeBSD on x86 (#163) 2021-07-02 15:37:03 +02:00
5492c4c561 CPU features for AMD (#165) 2021-06-30 12:38:56 +02:00
b3ef4ef49d Avoid leaking internal headers for ppc (#164) 2021-06-30 11:51:26 +02:00
001faefdc3 fix: Return default value from ‘GetCacheTypeString’ (#162)
The build fails with following message when -Werror
and -Werror=return-type are enabled.

In function ‘GetCacheTypeString’:
	error: control reaches end of non-void function [-Werror=return-type]

Simple fix is to return explicitly communicate to
the compiler that certain block is not reachable.
2021-06-25 10:28:26 +02:00
646b80fa3a [NFC] refactor the code so it's easier to understand the execution flow (#161) 2021-06-23 14:21:05 +00:00
108f3d9eca Fix #140 Atom processor detected as X86_UNKNOWN (#160) 2021-06-22 11:12:02 +02:00
bc2846e78f Detect AVX512 on Darwin use GetDarwinSysCtlByName("hw.optional.avx512f") (#153) 2021-05-21 11:14:50 +02:00
d35e2f38eb Detect Intel's Multi-Precision Add-Carry Instruction Extensions (#157) 2021-05-21 10:47:32 +02:00
7ed0b0e50e Detect Zen 3 (K19) cpus (#152)
Co-authored-by: natanbc <natanbc@users.noreply.github.com>
2021-02-25 21:47:39 +01:00
e2f6dea65f Update AArch64 features to Linux 5.10 (#149)
Added feature: MTE.
2020-12-15 13:28:53 +01:00
cdab59af76 [NFC] Simplify build by removing inl files. (#139) 2020-10-13 13:05:04 +02:00
9a8f04b24c [NFC] Generate separate tables via macro (#137)
This is a non functional change, it allows:
 - Getting rid of `unix_features_aggregator`
 - Have a single blob describing the features
 - Fix wrong mocking of `hwcaps`

Downside: abuse of macros makes the code slightly magical and harder to understand.
It think it's still an improvement over the current situation as there's less repetition and less chances to get something wrong.
2020-10-12 09:50:35 +00:00
3cc8f310d9 [NFC] Update copyright from Google Inc. to Google LLC 2020-10-12 08:55:20 +00:00
c0885fec9b docs: fix simple typo, intented -> intended (#138)
There is a small typo in src/utils/list_cpu_features.c.

Should read `intended` rather than `intented`.
2020-10-12 07:20:05 +00:00
e63405f118 Remove need for utsname (#136) 2020-10-09 20:40:06 +00:00
4795373db2 Fix SSE detection on non-AVX CPUs (#135)
Fixes #4. This is based on #115 with a few modifications:
 - Removed use of __builtin_cpu_supports since it relies on cpuid and doesn't improve on the current situation,
 - Added detection for all of sse, sse2, sse3, ssse3, sse4_1 and sse4_2,
 - Added tests for Atom, Nehalem, and P3 processors,

Thx to @gadoofou87 for providing the original PR.
It also removes the need for #92

* Fix SSE detection on non-AVX CPUs
* Fixes typo
* Mock OSX sysctlbyname in tests
* Also update other tests
* FakeCpu is reset between each tests
* Fix conflicting name on Windows
* Disable pre AVX cpu sse detection tests on Windows
* Guard OS specific code with macros
* Fix missing import for tests
* Fix wrong function prototype
* Fix wrong mocking of P3 on Windows
* Completely guard OS specific parts in x86 tests
* Store DWORD instead unsigned long for x86 tests
2020-10-09 15:20:25 +00:00
22a5362e11 [NFC] clang-format codebase (#134)
* [NFC] clang-format codebase

* revert to 80 char columns at the price of uglier table init

* Specifically disabling clang-format for table initialization
2020-09-23 09:52:20 +00:00
17ffb65117 detect AVX-512 FMA count (#125)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* second FMA features - incomplete and wrong

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* oops: use T/F not 2/1

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* implement SKX lookup

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

* cleanup AVX512 second FMA code

1) remove debug stuff
2) remove ICX - will add details when available

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* fix CPX detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove elses

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* remove curly braces from single-line conditional bodies

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* apply clang-format

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

Fixes #120
2020-09-22 07:29:46 +00:00
76dafc7e3b [NFC] Remove unused max_cpuid_leaf variable (#131) 2020-09-21 14:54:13 +02:00
33bd72c1bc detect future Intel AVX/AMX features (#124)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AVX512_BF16 and AVX512_VP2INTERSECT detection

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* correction for KNM features: s/4VBMI2/4FMAPS/g

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add AMX/TMUL bits from 319433-040

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fixes #128
2020-09-21 07:56:26 +00:00
e698327713 add future Intel microarchitectures (#123)
* add Ice Lake Server and Sapphire Rapids models

The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html

Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>

* Tiger Lake; Ice Lake NNP-I; SPR string

Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>

* add Intel copyright

Fix #127
2020-09-21 07:54:58 +00:00
73d10ad25b Update features for AArch64 to Linux 5.8 (#122)
This adds the following features: dcpodp, sve2, sveaes, svepmull,
svebitperm, svesha3, svesm4, flagm2, frint, svei8mm, svef32mm,
svef64mm, svebf16, i8mm, bf16, dgh and rng.

With these, all features used by Linux 5.8 on AArch64 is supported.

Fixes #126
2020-09-21 07:50:38 +00:00
339bfd32be Add OsSupport structure 2020-03-12 10:58:41 +00:00