* Fix getauxval comment (API 18 not 20)
getauxval is available in Android starting with API 18, not 20.
The comment about __ANDROID_API__ appears to have been copied from the
NDK's cpufeatures, which always uses dlopen/dlsym and doesn't assume it
can directly call getauxval, even if __ANDROID_API__ is new enough.
With this project, though, when __ANDROID_API__ is 18 or up, the
CMakeLists.txt file would detect that getauxval is available and define
HAVE_STRONG_GETAUXVAL.
* Broaden Qualcomm Krait idiv workaround
Some Qualcomm Krait CPUs have IDIV support but the kernel doesn't
report it. Previously, this code looked for two CPUs:
- 0x510006F2 (0x51/'Q', variant 0, part 0x06f, rev 2)
- 0x510006F3 (0x51/'Q', variant 0, part 0x06f, rev 3)
This check misses my 2013 Nexus 7 device, which has this CPU ID:
- 0x511006f0 (0x51/'Q', variant 1, part 0x06f, rev 0)
My Nexus 7 device doesn't report idiv through AT_HWCAP or through
/proc/cpuinfo (AT_HWCAP is 0x1b0d7).
Expand the check to anything with:
- implementer 0x51
- architecture 7
- part 0x4d or 0x6f
Part 0x4d appears to be a dual-core Krait (e.g. see
https://crbug.com/341598#c43).
This new matching behavior is a subset of what the upstream kernel
does (patch[1] contributed by CodeAurora), and also closely matches the
behavior of pytorch/cpuinfo.
[1] 120ecfafab
This patch reads the most important cpuid leaves and stores the data in
a struct. A followup patch will inline micro architecture detection and
brand string inside X86Info so we don't have to call `ReadLeaves` multiple
times. This wil allow further simplification of `HasSecondFMA` and help
fix https://github.com/google/cpu_features/issues/200.
Since buffers are a few tens of bytes there is no need for optimized memfunctions. For compile time sizes, the compiler will generate optimal code already.
This commit helps with platform code separation (fixes#3). It should also help with the build as we can simply include all `impl_*.c` files regardless of OS / arch.
Note: this patch contains breaking changes in `include/cpu_features_macros.h`
- `CPU_FEATURES_OS_LINUX_OR_ANDROID` does not exist anymore
- `CPU_FEATURES_OS_FREEBSD`, `CPU_FEATURES_OS_ANDROID` and `CPU_FEATURES_OS_LINUX` are now mutually exclusive (i.e. `CPU_FEATURES_OS_ANDROID` does not imply `CPU_FEATURES_OS_LINUX`)
- `CPU_FEATURES_OS_DARWIN` has been renamed into `CPU_FEATURES_OS_MACOS` to be able to target non-Mac Apple products (IOS, TV, WATCH). They are now targetable with `CPU_FEATURES_OS_IPHONE`. This matches Apple naming convention described in [this stackoverflow](https://stackoverflow.com/a/49560690).
The build fails with following message when -Werror
and -Werror=return-type are enabled.
In function ‘GetCacheTypeString’:
error: control reaches end of non-void function [-Werror=return-type]
Simple fix is to return explicitly communicate to
the compiler that certain block is not reachable.
This is a non functional change, it allows:
- Getting rid of `unix_features_aggregator`
- Have a single blob describing the features
- Fix wrong mocking of `hwcaps`
Downside: abuse of macros makes the code slightly magical and harder to understand.
It think it's still an improvement over the current situation as there's less repetition and less chances to get something wrong.
Fixes#4. This is based on #115 with a few modifications:
- Removed use of __builtin_cpu_supports since it relies on cpuid and doesn't improve on the current situation,
- Added detection for all of sse, sse2, sse3, ssse3, sse4_1 and sse4_2,
- Added tests for Atom, Nehalem, and P3 processors,
Thx to @gadoofou87 for providing the original PR.
It also removes the need for #92
* Fix SSE detection on non-AVX CPUs
* Fixes typo
* Mock OSX sysctlbyname in tests
* Also update other tests
* FakeCpu is reset between each tests
* Fix conflicting name on Windows
* Disable pre AVX cpu sse detection tests on Windows
* Guard OS specific code with macros
* Fix missing import for tests
* Fix wrong function prototype
* Fix wrong mocking of P3 on Windows
* Completely guard OS specific parts in x86 tests
* Store DWORD instead unsigned long for x86 tests
* [NFC] clang-format codebase
* revert to 80 char columns at the price of uglier table init
* Specifically disabling clang-format for table initialization
* add Ice Lake Server and Sapphire Rapids models
The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>
* Tiger Lake; Ice Lake NNP-I; SPR string
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* second FMA features - incomplete and wrong
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* oops: use T/F not 2/1
Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>
* implement SKX lookup
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* add Intel copyright
* cleanup AVX512 second FMA code
1) remove debug stuff
2) remove ICX - will add details when available
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* fix CPX detection
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* remove elses
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* remove curly braces from single-line conditional bodies
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* apply clang-format
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
Fixes#120
* add Ice Lake Server and Sapphire Rapids models
The information contained in this commit was obtained from
"Intel® Architecture Instruction Set Extensions and Future Features Programming Reference" document 319433-040 from
https://software.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Signed-off-by: Jeff Hammond <jeff.r.hammond@intel.com>
* Tiger Lake; Ice Lake NNP-I; SPR string
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* add AVX512_BF16 and AVX512_VP2INTERSECT detection
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* correction for KNM features: s/4VBMI2/4FMAPS/g
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* add AMX/TMUL bits from 319433-040
Signed-off-by: Hammond, Jeff R <jeff.r.hammond@intel.com>
* add Intel copyright
Fixes#128
This adds the following features: dcpodp, sve2, sveaes, svepmull,
svebitperm, svesha3, svesm4, flagm2, frint, svei8mm, svef32mm,
svef64mm, svebf16, i8mm, bf16, dgh and rng.
With these, all features used by Linux 5.8 on AArch64 is supported.
Fixes#126
