Artem Alekseev
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3ee4a9e801
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Support x86 DCA and SS features (#76)
* Add dca and ss features
* Remove trailing white spaces
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2019-06-19 15:06:05 +02:00 |
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Dr.-Ing. Patrick Siegl
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367bc42116
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Support x86 features: FPU, TSC, CX8, CLFSH, MMX, VAES, HLE, RTM, RDSEED, CLFLUSHOPT, CLWB, SSE, SSE2, SSE3, PCLMULQDQ (#73)
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2019-06-13 11:53:39 +02:00 |
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Guillaume Chatelet
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d395dfa026
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Add x86 missing feature detections for ndk_compat (#58)
One more step towards #47.
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2019-01-22 13:19:42 +01:00 |
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Guillaume Chatelet
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4155ee7e36
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Guarding header use with architecture (#56)
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2019-01-18 13:38:22 +01:00 |
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Guillaume Chatelet
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9b872ce0b2
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Add cx16 (cmpxchg16b) cpuid flag. Fixes #30
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2018-03-13 10:58:42 +01:00 |
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Patrik Fiedler
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3ee0d62e87
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detect intel sgx and smx cpu features for the x86 arch
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2018-02-13 11:16:48 +01:00 |
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Guillaume Chatelet
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e419573d10
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Use CPU_FEATURES_ prefix for namespace macros.
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2018-02-12 16:15:15 +01:00 |
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Guillaume Chatelet
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11e3e20496
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Reverting 338484f6f2176c3d8ede0ed2f3fbd6cf1eb0274c. Fixes #2
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2018-02-09 08:55:11 +01:00 |
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Guillaume Chatelet
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1d6ba6139c
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Merge pull request #5 from bsurmanski/patch-1
Fix spelling mistake for 'Cannon Lake'
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2018-02-08 16:34:15 +01:00 |
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Guillaume Chatelet
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338484f6f2
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Fixes #2 - vpclmulqdq should be pclmulqdq.
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2018-02-08 11:35:31 +01:00 |
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Brandon Surmanski
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efcc49a493
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Fix spelling mistake for 'Cannon Lake'
See:
https://www.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/platform-codenames.html
https://en.wikipedia.org/wiki/Cannon_Lake_(microarchitecture)
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2018-02-07 11:07:00 -08:00 |
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Guillaume Chatelet
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8e58ef0d2b
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Removing THIRD_PARTY_ from C headers.
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2018-02-01 10:38:48 +01:00 |
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Guillaume Chatelet
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439d371594
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Adding code. Closes #0.
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2018-02-01 10:03:09 +01:00 |
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