|
|
3ee4a9e801
|
Support x86 DCA and SS features (#76)
* Add dca and ss features
* Remove trailing white spaces
|
2019-06-19 15:06:05 +02:00 |
|
|
|
367bc42116
|
Support x86 features: FPU, TSC, CX8, CLFSH, MMX, VAES, HLE, RTM, RDSEED, CLFLUSHOPT, CLWB, SSE, SSE2, SSE3, PCLMULQDQ (#73)
|
2019-06-13 11:53:39 +02:00 |
|
|
|
d395dfa026
|
Add x86 missing feature detections for ndk_compat (#58)
One more step towards #47.
|
2019-01-22 13:19:42 +01:00 |
|
|
|
4155ee7e36
|
Guarding header use with architecture (#56)
|
2019-01-18 13:38:22 +01:00 |
|
|
|
9b872ce0b2
|
Add cx16 (cmpxchg16b) cpuid flag. Fixes #30
|
2018-03-13 10:58:42 +01:00 |
|
|
|
3ee0d62e87
|
detect intel sgx and smx cpu features for the x86 arch
|
2018-02-13 11:16:48 +01:00 |
|
|
|
e419573d10
|
Use CPU_FEATURES_ prefix for namespace macros.
|
2018-02-12 16:15:15 +01:00 |
|
|
|
11e3e20496
|
Reverting 338484f6f2. Fixes #2
|
2018-02-09 08:55:11 +01:00 |
|
|
|
1d6ba6139c
|
Merge pull request #5 from bsurmanski/patch-1
Fix spelling mistake for 'Cannon Lake'
|
2018-02-08 16:34:15 +01:00 |
|
|
|
338484f6f2
|
Fixes #2 - vpclmulqdq should be pclmulqdq.
|
2018-02-08 11:35:31 +01:00 |
|
|
|
efcc49a493
|
Fix spelling mistake for 'Cannon Lake'
See:
https://www.intel.com/content/www/us/en/design/products-and-solutions/processors-and-chipsets/platform-codenames.html
https://en.wikipedia.org/wiki/Cannon_Lake_(microarchitecture)
|
2018-02-07 11:07:00 -08:00 |
|
|
|
8e58ef0d2b
|
Removing THIRD_PARTY_ from C headers.
|
2018-02-01 10:38:48 +01:00 |
|
|
|
439d371594
|
Adding code. Closes #0.
|
2018-02-01 10:03:09 +01:00 |
|
