mirror of
https://github.com/google/cpu_features.git
synced 2025-04-28 07:23:37 +02:00
433 lines
13 KiB
C
433 lines
13 KiB
C
// Copyright 2017 Google Inc.
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "cpuinfo_x86.h"
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#include "internal/bit_utils.h"
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#include "internal/cpuid_x86.h"
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#include <stdbool.h>
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#include <string.h>
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static const Leaf kEmptyLeaf;
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static Leaf SafeCpuId(uint32_t max_cpuid_leaf, uint32_t leaf_id) {
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if (leaf_id <= max_cpuid_leaf) {
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return CpuId(leaf_id);
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} else {
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return kEmptyLeaf;
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}
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}
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#define MASK_XMM 0x2
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#define MASK_YMM 0x4
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#define MASK_MASKREG 0x20
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#define MASK_ZMM0_15 0x40
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#define MASK_ZMM16_31 0x80
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static bool HasMask(uint32_t value, uint32_t mask) {
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return (value & mask) == mask;
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}
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// Checks that operating system saves and restores xmm registers during context
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// switches.
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static bool HasXmmOsXSave(uint32_t xcr0_eax) {
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return HasMask(xcr0_eax, MASK_XMM);
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}
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// Checks that operating system saves and restores ymm registers during context
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// switches.
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static bool HasYmmOsXSave(uint32_t xcr0_eax) {
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return HasMask(xcr0_eax, MASK_XMM | MASK_YMM);
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}
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// Checks that operating system saves and restores zmm registers during context
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// switches.
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static bool HasZmmOsXSave(uint32_t xcr0_eax) {
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return HasMask(xcr0_eax, MASK_XMM | MASK_YMM | MASK_MASKREG | MASK_ZMM0_15 |
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MASK_ZMM16_31);
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}
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static void SetVendor(const Leaf leaf, char* const vendor) {
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*(uint32_t*)(vendor) = leaf.ebx;
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*(uint32_t*)(vendor + 4) = leaf.edx;
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*(uint32_t*)(vendor + 8) = leaf.ecx;
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vendor[12] = '\0';
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}
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static int IsVendor(const Leaf leaf, const char* const name) {
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const uint32_t ebx = *(const uint32_t*)(name);
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const uint32_t edx = *(const uint32_t*)(name + 4);
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const uint32_t ecx = *(const uint32_t*)(name + 8);
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return leaf.ebx == ebx && leaf.ecx == ecx && leaf.edx == edx;
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}
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// Reference https://en.wikipedia.org/wiki/CPUID.
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static void ParseCpuId(const uint32_t max_cpuid_leaf, X86Info* info) {
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const Leaf leaf_1 = SafeCpuId(max_cpuid_leaf, 1);
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const Leaf leaf_7 = SafeCpuId(max_cpuid_leaf, 7);
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const bool have_xsave = IsBitSet(leaf_1.ecx, 26);
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const bool have_osxsave = IsBitSet(leaf_1.ecx, 27);
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const uint32_t xcr0_eax = (have_xsave && have_osxsave) ? GetXCR0Eax() : 0;
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const bool have_sse_os_support = HasXmmOsXSave(xcr0_eax);
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const bool have_avx_os_support = HasYmmOsXSave(xcr0_eax);
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const bool have_avx512_os_support = HasZmmOsXSave(xcr0_eax);
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const uint32_t family = ExtractBitRange(leaf_1.eax, 11, 8);
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const uint32_t extended_family = ExtractBitRange(leaf_1.eax, 27, 20);
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const uint32_t model = ExtractBitRange(leaf_1.eax, 7, 4);
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const uint32_t extended_model = ExtractBitRange(leaf_1.eax, 19, 16);
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X86Features* const features = &info->features;
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info->family = extended_family + family;
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info->model = (extended_model << 4) + model;
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info->stepping = ExtractBitRange(leaf_1.eax, 3, 0);
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features->aes = IsBitSet(leaf_1.ecx, 25);
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features->erms = IsBitSet(leaf_7.ebx, 9);
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features->f16c = IsBitSet(leaf_1.ecx, 29);
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features->bmi1 = IsBitSet(leaf_7.ebx, 3);
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features->bmi2 = IsBitSet(leaf_7.ebx, 8);
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features->vpclmulqdq = IsBitSet(leaf_7.ecx, 10);
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if (have_sse_os_support) {
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features->ssse3 = IsBitSet(leaf_1.ecx, 9);
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features->sse4_1 = IsBitSet(leaf_1.ecx, 19);
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features->sse4_2 = IsBitSet(leaf_1.ecx, 20);
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}
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if (have_avx_os_support) {
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features->fma3 = IsBitSet(leaf_1.ecx, 12);
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features->avx = IsBitSet(leaf_1.ecx, 28);
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features->avx2 = IsBitSet(leaf_7.ebx, 5);
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}
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if (have_avx512_os_support) {
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features->avx512f = IsBitSet(leaf_7.ebx, 16);
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features->avx512cd = IsBitSet(leaf_7.ebx, 28);
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features->avx512er = IsBitSet(leaf_7.ebx, 27);
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features->avx512pf = IsBitSet(leaf_7.ebx, 26);
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features->avx512bw = IsBitSet(leaf_7.ebx, 30);
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features->avx512dq = IsBitSet(leaf_7.ebx, 17);
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features->avx512vl = IsBitSet(leaf_7.ebx, 31);
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features->avx512ifma = IsBitSet(leaf_7.ebx, 21);
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features->avx512vbmi = IsBitSet(leaf_7.ecx, 1);
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features->avx512vbmi2 = IsBitSet(leaf_7.ecx, 6);
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features->avx512vnni = IsBitSet(leaf_7.ecx, 11);
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features->avx512bitalg = IsBitSet(leaf_7.ecx, 12);
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features->avx512vpopcntdq = IsBitSet(leaf_7.ecx, 14);
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features->avx512_4vnniw = IsBitSet(leaf_7.edx, 2);
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features->avx512_4vbmi2 = IsBitSet(leaf_7.edx, 3);
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}
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}
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static const X86Info kEmptyX86Info;
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X86Info GetX86Info(void) {
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X86Info info = kEmptyX86Info;
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const Leaf leaf_0 = CpuId(0);
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const uint32_t max_cpuid_leaf = leaf_0.eax;
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SetVendor(leaf_0, info.vendor);
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if (IsVendor(leaf_0, "GenuineIntel") || IsVendor(leaf_0, "AuthenticAMD")) {
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ParseCpuId(max_cpuid_leaf, &info);
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}
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return info;
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}
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#define CPUID(FAMILY, MODEL) (((FAMILY & 0xFF) << 8) | (MODEL & 0xFF))
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X86Microarchitecture GetX86Microarchitecture(const X86Info* info) {
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if (memcmp(info->vendor, "GenuineIntel", sizeof(info->vendor)) == 0) {
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switch (CPUID(info->family, info->model)) {
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case CPUID(0x06, 0x35):
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case CPUID(0x06, 0x36):
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// https://en.wikipedia.org/wiki/Bonnell_(microarchitecture)
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return INTEL_ATOM_BNL;
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case CPUID(0x06, 0x37):
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case CPUID(0x06, 0x4C):
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// https://en.wikipedia.org/wiki/Silvermont
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return INTEL_ATOM_SMT;
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case CPUID(0x06, 0x5C):
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// https://en.wikipedia.org/wiki/Goldmont
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return INTEL_ATOM_GMT;
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case CPUID(0x06, 0x0F):
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case CPUID(0x06, 0x16):
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// https://en.wikipedia.org/wiki/Intel_Core_(microarchitecture)
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return INTEL_CORE;
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case CPUID(0x06, 0x17):
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case CPUID(0x06, 0x1D):
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// https://en.wikipedia.org/wiki/Penryn_(microarchitecture)
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return INTEL_PNR;
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case CPUID(0x06, 0x1A):
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case CPUID(0x06, 0x1E):
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case CPUID(0x06, 0x1F):
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case CPUID(0x06, 0x2E):
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// https://en.wikipedia.org/wiki/Nehalem_(microarchitecture)
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return INTEL_NHM;
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case CPUID(0x06, 0x25):
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case CPUID(0x06, 0x2C):
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case CPUID(0x06, 0x2F):
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// https://en.wikipedia.org/wiki/Westmere_(microarchitecture)
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return INTEL_WSM;
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case CPUID(0x06, 0x2A):
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case CPUID(0x06, 0x2D):
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// https://en.wikipedia.org/wiki/Sandy_Bridge#Models_and_steppings
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return INTEL_SNB;
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case CPUID(0x06, 0x3A):
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case CPUID(0x06, 0x3E):
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// https://en.wikipedia.org/wiki/Ivy_Bridge_(microarchitecture)#Models_and_steppings
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return INTEL_IVB;
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case CPUID(0x06, 0x3C):
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case CPUID(0x06, 0x3F):
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case CPUID(0x06, 0x45):
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case CPUID(0x06, 0x46):
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// https://en.wikipedia.org/wiki/Haswell_(microarchitecture)
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return INTEL_HSW;
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case CPUID(0x06, 0x3D):
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case CPUID(0x06, 0x47):
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case CPUID(0x06, 0x4F):
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case CPUID(0x06, 0x56):
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// https://en.wikipedia.org/wiki/Broadwell_(microarchitecture)
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return INTEL_BDW;
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case CPUID(0x06, 0x4E):
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case CPUID(0x06, 0x55):
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case CPUID(0x06, 0x5E):
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// https://en.wikipedia.org/wiki/Skylake_(microarchitecture)
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return INTEL_SKL;
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case CPUID(0x06, 0x8E):
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case CPUID(0x06, 0x9E):
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// https://en.wikipedia.org/wiki/Kaby_Lake
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return INTEL_KBL;
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default:
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return X86_UNKNOWN;
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}
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}
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if (memcmp(info->vendor, "AuthenticAMD", sizeof(info->vendor)) == 0) {
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switch (info->family) {
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// https://en.wikipedia.org/wiki/List_of_AMD_CPU_microarchitectures
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case 0x0F:
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return AMD_HAMMER;
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case 0x10:
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return AMD_K10;
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case 0x14:
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return AMD_BOBCAT;
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case 0x15:
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return AMD_BULLDOZER;
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case 0x16:
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return AMD_JAGUAR;
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case 0x17:
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return AMD_ZEN;
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default:
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return X86_UNKNOWN;
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}
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}
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return X86_UNKNOWN;
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}
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static void SetString(const uint32_t max_cpuid_ext_leaf, const uint32_t leaf_id,
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char* buffer) {
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const Leaf leaf = SafeCpuId(max_cpuid_ext_leaf, leaf_id);
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// We allow calling memcpy from SetString which is only called when requesting
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// X86BrandString.
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memcpy(buffer, &leaf, sizeof(Leaf));
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}
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void FillX86BrandString(char brand_string[49]) {
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const Leaf leaf_ext_0 = CpuId(0x80000000);
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const uint32_t max_cpuid_leaf_ext = leaf_ext_0.eax;
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SetString(max_cpuid_leaf_ext, 0x80000002, brand_string);
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SetString(max_cpuid_leaf_ext, 0x80000003, brand_string + 16);
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SetString(max_cpuid_leaf_ext, 0x80000004, brand_string + 32);
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brand_string[48] = '\0';
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}
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////////////////////////////////////////////////////////////////////////////////
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// Introspection functions
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int GetX86FeaturesEnumValue(const X86Features* features,
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X86FeaturesEnum value) {
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switch (value) {
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case X86_AES:
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return features->aes;
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case X86_ERMS:
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return features->erms;
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case X86_F16C:
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return features->f16c;
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case X86_FMA3:
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return features->fma3;
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case X86_VPCLMULQDQ:
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return features->vpclmulqdq;
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case X86_BMI1:
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return features->bmi1;
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case X86_BMI2:
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return features->bmi2;
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case X86_SSSE3:
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return features->ssse3;
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case X86_SSE4_1:
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return features->sse4_1;
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case X86_SSE4_2:
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return features->sse4_2;
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case X86_AVX:
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return features->avx;
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case X86_AVX2:
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return features->avx2;
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case X86_AVX512F:
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return features->avx512f;
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case X86_AVX512CD:
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return features->avx512cd;
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case X86_AVX512ER:
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return features->avx512er;
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case X86_AVX512PF:
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return features->avx512pf;
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case X86_AVX512BW:
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return features->avx512bw;
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case X86_AVX512DQ:
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return features->avx512dq;
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case X86_AVX512VL:
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return features->avx512vl;
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case X86_AVX512IFMA:
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return features->avx512ifma;
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case X86_AVX512VBMI:
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return features->avx512vbmi;
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case X86_AVX512VBMI2:
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return features->avx512vbmi2;
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case X86_AVX512VNNI:
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return features->avx512vnni;
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case X86_AVX512BITALG:
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return features->avx512bitalg;
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case X86_AVX512VPOPCNTDQ:
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return features->avx512vpopcntdq;
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case X86_AVX512_4VNNIW:
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return features->avx512_4vnniw;
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case X86_AVX512_4VBMI2:
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return features->avx512_4vbmi2;
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case X86_LAST_:
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break;
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}
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return false;
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}
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const char* GetX86FeaturesEnumName(X86FeaturesEnum value) {
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switch (value) {
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case X86_AES:
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return "aes";
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case X86_ERMS:
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return "erms";
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case X86_F16C:
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return "f16c";
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case X86_FMA3:
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return "fma3";
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case X86_VPCLMULQDQ:
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return "vpclmulqdq";
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case X86_BMI1:
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return "bmi1";
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case X86_BMI2:
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return "bmi2";
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case X86_SSSE3:
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return "ssse3";
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case X86_SSE4_1:
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return "sse4_1";
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case X86_SSE4_2:
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return "sse4_2";
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case X86_AVX:
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return "avx";
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case X86_AVX2:
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return "avx2";
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case X86_AVX512F:
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return "avx512f";
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case X86_AVX512CD:
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return "avx512cd";
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case X86_AVX512ER:
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return "avx512er";
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case X86_AVX512PF:
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return "avx512pf";
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case X86_AVX512BW:
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return "avx512bw";
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case X86_AVX512DQ:
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return "avx512dq";
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case X86_AVX512VL:
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return "avx512vl";
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case X86_AVX512IFMA:
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return "avx512ifma";
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case X86_AVX512VBMI:
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return "avx512vbmi";
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case X86_AVX512VBMI2:
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return "avx512vbmi2";
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case X86_AVX512VNNI:
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return "avx512vnni";
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case X86_AVX512BITALG:
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return "avx512bitalg";
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case X86_AVX512VPOPCNTDQ:
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return "avx512vpopcntdq";
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case X86_AVX512_4VNNIW:
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return "avx512_4vnniw";
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case X86_AVX512_4VBMI2:
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return "avx512_4vbmi2";
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case X86_LAST_:
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break;
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}
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return "unknown_feature";
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}
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const char* GetX86MicroarchitectureName(X86Microarchitecture uarch) {
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switch (uarch) {
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case X86_UNKNOWN:
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return "X86_UNKNOWN";
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case INTEL_CORE:
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return "INTEL_CORE";
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case INTEL_PNR:
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return "INTEL_PNR";
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case INTEL_NHM:
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return "INTEL_NHM";
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case INTEL_ATOM_BNL:
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return "INTEL_ATOM_BNL";
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case INTEL_WSM:
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return "INTEL_WSM";
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case INTEL_SNB:
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return "INTEL_SNB";
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case INTEL_IVB:
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return "INTEL_IVB";
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case INTEL_ATOM_SMT:
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return "INTEL_ATOM_SMT";
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case INTEL_HSW:
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return "INTEL_HSW";
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case INTEL_BDW:
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return "INTEL_BDW";
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case INTEL_SKL:
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return "INTEL_SKL";
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case INTEL_ATOM_GMT:
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return "INTEL_ATOM_GMT";
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case INTEL_KBL:
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return "INTEL_KBL";
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case INTEL_CFL:
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return "INTEL_CFL";
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case INTEL_CNL:
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return "INTEL_CNL";
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case AMD_HAMMER:
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return "AMD_HAMMER";
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case AMD_K10:
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return "AMD_K10";
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case AMD_BOBCAT:
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return "AMD_BOBCAT";
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case AMD_BULLDOZER:
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return "AMD_BULLDOZER";
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case AMD_JAGUAR:
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return "AMD_JAGUAR";
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case AMD_ZEN:
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return "AMD_ZEN";
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}
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return "unknown microarchitecture";
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}
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