1
0
mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 22:43:17 +02:00

Add Intel Gigabit NIC SPI flashing support

Tested on a 82541PI (0x8086, 0x107c) using 32-bit hardware.

The last line in nicintel_request_spibus() could be changed so that FL_BUSY
is used instead.

Shortened sample log:
[...]
Found "Intel 82541PI Gigabit Ethernet Controller" (8086:107c, BDF 01:03.0).
Found chip "ST M25P10.RES" (128 KB, SPI) at physical address 0xfffe0000.
Multiple flash chips were detected: M25P05.RES M25P10.RES
Please specify which chip to use with the -c <chipname> option.
[...]

Corresponding to flashrom svn r1151.

Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
Idwer Vollering
2010-09-03 18:21:21 +00:00
committed by Uwe Hermann
parent 67db2eb92c
commit 004f4b7954
8 changed files with 263 additions and 4 deletions

View File

@ -121,9 +121,13 @@ else
ifeq ($(CONFIG_INTERNAL), yes)
override CONFIG_BITBANG_SPI = yes
else
ifeq ($(CONFIG_NICINTEL_SPI), yes)
override CONFIG_BITBANG_SPI = yes
else
CONFIG_BITBANG_SPI ?= no
endif
endif
endif
# Always enable 3Com NICs for now.
CONFIG_NIC3COM ?= yes
@ -153,6 +157,9 @@ CONFIG_NICREALTEK ?= yes
# Disable National Semiconductor NICs until support is complete and tested.
CONFIG_NICNATSEMI ?= no
# Always enable SPI on Intel NICs for now.
CONFIG_NICINTEL_SPI ?= yes
# Always enable Bus Pirate SPI for now.
CONFIG_BUSPIRATE_SPI ?= yes
@ -244,6 +251,12 @@ PROGRAMMER_OBJS += nicnatsemi.o
NEED_PCI := yes
endif
ifeq ($(CONFIG_NICINTEL_SPI), yes)
FEATURE_CFLAGS += -D'CONFIG_NICINTEL_SPI=1'
PROGRAMMER_OBJS += nicintel_spi.o
NEED_PCI := yes
endif
ifeq ($(CONFIG_BUSPIRATE_SPI), yes)
FEATURE_CFLAGS += -D'CONFIG_BUSPIRATE_SPI=1'
PROGRAMMER_OBJS += buspirate_spi.o