openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-07-01 14:11:15 +02:00
Code Issues Releases Wiki Activity

Refine handling of spi_write_enable() failures to fix chip erases on ichspi

Browse Source 
Until the ICH SPI driver can handle preopcodes as standalone opcodes,
we should handle such special opcode failure gracefully on ICH and
compatible chipsets.

This fixes chip erase on almost all ICH+VIA SPI masters.

Thanks to Ali Nadalizadeh for helping track down this bug!

Corresponding to flashrom svn r484.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Carl-Daniel Hailfinger
2009-05-09 02:09:45 +00:00
parent c312920864
commit 03adbe1269
4 changed files with 54 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
wbsio_spi.c
View File

@ -189,6 +189,7 @@ int wbsio_spi_read(struct flashchip *flash, uint8_t *buf)
int wbsio_spi_write(struct flashchip *flash, uint8_t *buf)
{
int pos, size = flash->total_size * 1024;
int result;
if (flash->total_size > 1024) {
fprintf(stderr, "%s: Winbond saved on 4 register bits so max chip size is 1024 KB!\n", __func__);
@ -196,7 +197,9 @@ int wbsio_spi_write(struct flashchip *flash, uint8_t *buf)
}
flash->erase(flash);
spi_write_enable();
result = spi_write_enable();
if (result)
return result;
for (pos = 0; pos < size; pos++) {
spi_byte_program(pos, buf[pos]);
while (spi_read_status_register() & JEDEC_RDSR_BIT_WIP)