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flashchips: Correct feature_bits for MX25L128*

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In CB:81792 (CL:5471748) we add write-protect support for MX25L12833F,
MX25L12835F/MX25L12873F, and MX25L12845E/MX25L12865E.

However, that CL contained a bug that it didn't set the feature_bits
correctly. We need to add:

* Add FEATURE_CFGR and FEATURE_SCUR for MX25L12833F
* Add FEATURE_CFGR and FEATURE_SCUR for MX25L12835F/MX25L12873F
* Add FEATURE_SCUR for MX25L12845E/MX25L12865E

BUG=b:332486637
TEST=In a host connect to ADL-n ChromeOS via servo, with this patch,
     flashrom -p raiden_debug_spi:target=AP,custom_rst=true
     ,serial=$(dut-control -o ccd_serialname -p 9996) --wp-status
     returns correct WP status.
TEST=without this patch, returns error with
     "Cannot read SECURITY: unsupported by chip"

Change-Id: I001cde6816bd099317bc9c23904c5fcbe6003241
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/82605
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Hsuan Ting Chen 2024-05-22 17:45:02 +08:00 committed by Anastasia Klimchuk
parent 35a2168c32
commit 066890377d
1 changed files with 3 additions and 3 deletions
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6
flashchips.c
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@ -9209,7 +9209,7 @@ const struct flashchip flashchips[] = {
.total_size = 16384, .total_size = 16384,
.page_size = 256, .page_size = 256,
/* OTP: 1KB total; enter 0xB1, exit 0xC1 */ /* OTP: 1KB total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR | FEATURE_SCUR,
.tested = TEST_OK_PREWB, .tested = TEST_OK_PREWB,
.probe = PROBE_SPI_RDID, .probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO, .probe_timing = TIMING_ZERO,
@ -9256,7 +9256,7 @@ const struct flashchip flashchips[] = {
.total_size = 16384, .total_size = 16384,
.page_size = 256, .page_size = 256,
/* OTP: 512B total; enter 0xB1, exit 0xC1 */ /* OTP: 512B total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_CFGR | FEATURE_SCUR,
.tested = TEST_OK_PREW, .tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID, .probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO, .probe_timing = TIMING_ZERO,
@ -9303,7 +9303,7 @@ const struct flashchip flashchips[] = {
.total_size = 16384, .total_size = 16384,
.page_size = 256, .page_size = 256,
/* OTP: 512B total; enter 0xB1, exit 0xC1 */ /* OTP: 512B total; enter 0xB1, exit 0xC1 */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP, .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_SCUR,
.tested = TEST_OK_PREW, .tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID, .probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO, .probe_timing = TIMING_ZERO,