From 078d24ef2feb59d1de3a0eb5f99010c999763758 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.h@gmx.de>
Date: Wed, 13 Dec 2017 00:44:45 +0100
Subject: [PATCH] ichspi: Fix 100 series PCH (Skylake) support

Pretty subtle missing `else` made flashrom treat Skylake like older
chipsets.

Change-Id: I14bf578964124d4677cb5dfca01c9d1b0d279c9c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reported-by: Youness Alaoui <kakaroto@kakaroto.homelinux.net>
Reviewed-on: https://review.coreboot.org/22832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
(cherry picked from commit 19eb0792b8439198d7ef0077b8f79f275fa39a9d)
Reviewed-on: https://review.coreboot.org/22944
---
 ichspi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ichspi.c b/ichspi.c
index 859d55f79..c7bda920b 100644
--- a/ichspi.c
+++ b/ichspi.c
@@ -1715,7 +1715,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
 		hwseq_data.addr_mask	= PCH100_FADDR_FLA;
 		hwseq_data.only_4k	= true;
 		hwseq_data.hsfc_fcycle	= PCH100_HSFC_FCYCLE;
-	} if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) {
+	} else if (ich_generation == CHIPSET_C620_SERIES_LEWISBURG) {
 		num_freg		= 12;	/* 12 MMIO regs, but 16 regions in FD spec */
 		num_pr			= 6;	/* Includes GPR0 */
 		reg_pr0			= PCH100_REG_FPR0;