mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-29 07:53:44 +02:00
chipset_enable.c: Mark Intel C224 as DEP
Tested on a Supermicro X10SLM+-F. The flash chip has been read, written, and erased many times without issue. Most boards with this chipset will have the ME region locked, hence the selection of DEP. Change-Id: I25126b94e691289a7b29dd81d5c864854a4e0245 Signed-off-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-on: https://review.coreboot.org/c/30361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
parent
e7cbfae69e
commit
099c8b2d5f
@ -1841,7 +1841,7 @@ const struct penable chipset_enables[] = {
|
|||||||
{0x8086, 0x8c51, NT, "Intel", "Lynx Point", enable_flash_pch8},
|
{0x8086, 0x8c51, NT, "Intel", "Lynx Point", enable_flash_pch8},
|
||||||
{0x8086, 0x8c52, NT, "Intel", "C222", enable_flash_pch8},
|
{0x8086, 0x8c52, NT, "Intel", "C222", enable_flash_pch8},
|
||||||
{0x8086, 0x8c53, NT, "Intel", "Lynx Point", enable_flash_pch8},
|
{0x8086, 0x8c53, NT, "Intel", "Lynx Point", enable_flash_pch8},
|
||||||
{0x8086, 0x8c54, NT, "Intel", "C224", enable_flash_pch8},
|
{0x8086, 0x8c54, DEP, "Intel", "C224", enable_flash_pch8},
|
||||||
{0x8086, 0x8c55, NT, "Intel", "Lynx Point", enable_flash_pch8},
|
{0x8086, 0x8c55, NT, "Intel", "Lynx Point", enable_flash_pch8},
|
||||||
{0x8086, 0x8c56, NT, "Intel", "C226", enable_flash_pch8},
|
{0x8086, 0x8c56, NT, "Intel", "C226", enable_flash_pch8},
|
||||||
{0x8086, 0x8c57, NT, "Intel", "Lynx Point", enable_flash_pch8},
|
{0x8086, 0x8c57, NT, "Intel", "Lynx Point", enable_flash_pch8},
|
||||||
|
Loading…
x
Reference in New Issue
Block a user