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ichspi: Split very long init function into two

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ich_init_spi is very long, but logically it can be split. Init
function detects the chipset and then the rest of operations depends
on the chipset.

Init function is more readable now, it consists of only a switch.

Initialisation of hwseq and swseq that used to happen in the
beginning of init function now moved to init_ich_default, because
hwseq and swseq are only used for chipsets served by init_ich_default.

BUG=b:204488958
TEST=Check that the following scenarios still behave properly:
1) probe-read-verify-erase section-write-reboot
on Intel octopus board with GD25LQ128C/GD25LQ128D/GD25LQ128E
2) probe and read on Panther Point (7 series PCH)
3) on machine with ich7 chipset, output from probe and read is
the same between master and this patch

Change-Id: I6789bc456a4878e6555831ae0b80ecbdbf62938b
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: Anastasia Klimchuk <aklm@chromium.org>
Tested-by: Nico Huber <nico.h@gmx.de>
Tested-by: Nicholas Chin <nic.c3.14@gmail.com>
Signed-off-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/58735
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Anastasia Klimchuk 2021-10-29 10:38:37 +11:00 committed by Nico Huber
parent e98b2d1184
commit 0d7767ecdb
1 changed files with 271 additions and 258 deletions
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99
ichspi.c
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@ -1713,7 +1713,46 @@ static const struct opaque_master opaque_master_ich_hwseq = {
.erase = ich_hwseq_block_erase,
};
int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
static int init_ich7_spi(void *spibar, enum ich_chipset ich_gen)
{
unsigned int i;
msg_pdbg("0x00: 0x%04x (SPIS)\n",
mmio_readw(spibar + 0));
msg_pdbg("0x02: 0x%04x (SPIC)\n",
mmio_readw(spibar + 2));
msg_pdbg("0x04: 0x%08x (SPIA)\n",
mmio_readl(spibar + 4));
ichspi_bbar = mmio_readl(spibar + 0x50);
msg_pdbg("0x50: 0x%08x (BBAR)\n",
ichspi_bbar);
msg_pdbg("0x54: 0x%04x (PREOP)\n",
mmio_readw(spibar + 0x54));
msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
mmio_readw(spibar + 0x56));
msg_pdbg("0x58: 0x%08x (OPMENU)\n",
mmio_readl(spibar + 0x58));
msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
mmio_readl(spibar + 0x5c));
for (i = 0; i < 3; i++) {
int offs;
offs = 0x60 + (i * 4);
msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs,
mmio_readl(spibar + offs), i);
}
if (mmio_readw(spibar) & (1 << 15)) {
msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
ichspi_lock = 1;
}
ich_init_opcodes(ich_gen);
ich_set_bbar(0, ich_gen);
register_spi_master(&spi_master_ich7, NULL);
return 0;
}
static int init_ich_default(void *spibar, enum ich_chipset ich_gen)
{
unsigned int i;
uint16_t tmp2;
@ -1729,9 +1768,6 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
} ich_spi_mode = ich_auto;
size_t num_freg, num_pr, reg_pr0;
ich_generation = ich_gen;
ich_spibar = spibar;
/* Moving registers / bits */
switch (ich_gen) {
case CHIPSET_100_SERIES_SUNRISE_POINT:
@ -1782,43 +1818,6 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
break;
}
switch (ich_gen) {
case CHIPSET_ICH7:
case CHIPSET_TUNNEL_CREEK:
case CHIPSET_CENTERTON:
msg_pdbg("0x00: 0x%04x (SPIS)\n",
mmio_readw(spibar + 0));
msg_pdbg("0x02: 0x%04x (SPIC)\n",
mmio_readw(spibar + 2));
msg_pdbg("0x04: 0x%08x (SPIA)\n",
mmio_readl(spibar + 4));
ichspi_bbar = mmio_readl(spibar + 0x50);
msg_pdbg("0x50: 0x%08x (BBAR)\n",
ichspi_bbar);
msg_pdbg("0x54: 0x%04x (PREOP)\n",
mmio_readw(spibar + 0x54));
msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
mmio_readw(spibar + 0x56));
msg_pdbg("0x58: 0x%08x (OPMENU)\n",
mmio_readl(spibar + 0x58));
msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
mmio_readl(spibar + 0x5c));
for (i = 0; i < 3; i++) {
int offs;
offs = 0x60 + (i * 4);
msg_pdbg("0x%02x: 0x%08x (PBR%u)\n", offs,
mmio_readl(spibar + offs), i);
}
if (mmio_readw(spibar) & (1 << 15)) {
msg_pwarn("WARNING: SPI Configuration Lockdown activated.\n");
ichspi_lock = 1;
}
ich_init_opcodes(ich_gen);
ich_set_bbar(0, ich_gen);
register_spi_master(&spi_master_ich7, NULL);
break;
case CHIPSET_ICH8:
default: /* Future version might behave the same */
arg = extract_programmer_param("ich_spi_mode");
if (arg && !strcmp(arg, "hwseq")) {
ich_spi_mode = ich_hwseq;
@ -2055,12 +2054,26 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
} else {
register_spi_master(&spi_master_ich9, NULL);
}
break;
}
return 0;
}
int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
{
ich_generation = ich_gen;
ich_spibar = spibar;
switch (ich_gen) {
case CHIPSET_ICH7:
case CHIPSET_TUNNEL_CREEK:
case CHIPSET_CENTERTON:
return init_ich7_spi(spibar, ich_gen);
case CHIPSET_ICH8:
default: /* Future version might behave the same */
return init_ich_default(spibar, ich_gen);
}
}
static const struct spi_master spi_master_via = {
.max_data_read = 16,
.max_data_write = 16,