Add Gemini Lake support

The SPI hardware is pretty much unchanged from Apollo Lake. However, the
IFD differs significantly enough to require special handling.

Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib5dcdf204166f44a8531c19b5f363b851d2ccd77
Reviewed-on: https://review.coreboot.org/c/flashrom/+/54276
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

chipset_enable.c

@@ -601,6 +601,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_400_SERIES_COMET_POINT:
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		reg_name = "BIOS_SPI_BC";
 		gcs = pci_read_long(dev, 0xdc);
 		bild = (gcs >> 7) & 1;
@@ -699,6 +700,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
 		boot_straps = boot_straps_pch8_lp;
 		break;
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		boot_straps = boot_straps_apl;
 		break;
 	case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
@@ -726,6 +728,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_400_SERIES_COMET_POINT:
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		bbs = (gcs >> 6) & 0x1;
 		break;
 	default:
@@ -976,6 +979,11 @@ static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
 	return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
 }
 
+static int enable_flash_glk(struct pci_dev *const dev, const char *const name)
+{
+	return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_GEMINI_LAKE);
+}
+
 /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
  * These have a distinctly different behavior compared to other Intel chipsets and hence are handled separately.
  *
@@ -2076,6 +2084,7 @@ const struct penable chipset_enables[] = {
 	{0x8086, 0xa2d2, B_S,    NT,  "Intel", "X299",				enable_flash_pch100},
 	{0x8086, 0x5ae8, B_S,    DEP, "Intel", "Apollo Lake",			enable_flash_apl},
 	{0x8086, 0x5af0, B_S,    DEP, "Intel", "Apollo Lake",			enable_flash_apl},
+	{0x8086, 0x31e8, B_S,    DEP, "Intel", "Gemini Lake",			enable_flash_glk},
 	{0x8086, 0xa303, B_S,    NT,  "Intel", "H310",				enable_flash_pch300},
 	{0x8086, 0xa304, B_S,    NT,  "Intel", "H370",				enable_flash_pch300},
 	{0x8086, 0xa305, B_S,    NT,  "Intel", "Z390",				enable_flash_pch300},

ich_descriptors.c

@@ -39,6 +39,7 @@ ssize_t ich_number_of_regions(const enum ich_chipset cs, const struct ich_desc_c
 {
 	switch (cs) {
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		return 6;
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
@@ -68,6 +69,7 @@ ssize_t ich_number_of_masters(const enum ich_chipset cs, const struct ich_desc_c
 	switch (cs) {
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		if (cont->NM <= MAX_NUM_MASTERS)
 			return cont->NM;
 		break;
@@ -104,7 +106,7 @@ void prettyprint_ich_chipset(enum ich_chipset cs)
 		"5 series Ibex Peak", "6 series Cougar Point", "7 series Panther Point",
 		"8 series Lynx Point", "Baytrail", "8 series Lynx Point LP", "8 series Wellsburg",
 		"9 series Wildcat Point", "9 series Wildcat Point LP", "100 series Sunrise Point",
-		"C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake",
+		"C620 series Lewisburg", "300 series Cannon Point", "Apollo Lake", "Gemini Lake",
 	};
 	if (cs < CHIPSET_ICH8 || cs - CHIPSET_ICH8 + 1 >= ARRAY_SIZE(chipset_names))
 		cs = 0;
@@ -198,7 +200,8 @@ static const char *pprint_density(enum ich_chipset cs, const struct ich_descript
 	case CHIPSET_C620_SERIES_LEWISBURG:
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_400_SERIES_COMET_POINT:
-	case CHIPSET_APOLLO_LAKE: {
+	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE: {
 		uint8_t size_enc;
 		if (idx == 0) {
 			size_enc = desc->component.dens_new.comp1_density;
@@ -269,6 +272,7 @@ static const char *pprint_freq(enum ich_chipset cs, uint8_t value)
 	case CHIPSET_400_SERIES_COMET_POINT:
 		return freq_str[1][value];
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		return freq_str[2][value];
 	case CHIPSET_ICH_UNKNOWN:
 	default:
@@ -286,6 +290,7 @@ void prettyprint_ich_descriptor_component(enum ich_chipset cs, const struct ich_
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_400_SERIES_COMET_POINT:
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		has_flill1 = true;
 		break;
 	default:
@@ -462,7 +467,7 @@ void prettyprint_ich_descriptor_master(const enum ich_chipset cs, const struct i
 					  desc->master.mstr[i].write & (1 << j) ? 'w' : ' ');
 			msg_pdbg2("\n");
 		}
-	} else if (cs == CHIPSET_APOLLO_LAKE) {
+	} else if (cs == CHIPSET_APOLLO_LAKE || cs == CHIPSET_GEMINI_LAKE) {
 		const char *const master_names[] = { "BIOS", "TXE", };
 		if (nm > (ssize_t)ARRAY_SIZE(master_names)) {
 			msg_pdbg2("%s: number of masters too high (%d).\n", __func__, desc->content.NM);
@@ -922,7 +927,9 @@ static enum ich_chipset guess_ich_chipset_from_content(const struct ich_desc_con
 		else if (content->ISL <= 16)
 			return CHIPSET_5_SERIES_IBEX_PEAK;
 		else if (content->FLMAP2 == 0) {
-			if (content->ISL != 19)
+			if (content->ISL == 23)
+				return CHIPSET_GEMINI_LAKE;
+			else if (content->ISL != 19)
 				msg_pwarn("Peculiar firmware descriptor, assuming Apollo Lake compatibility.\n");
 			return CHIPSET_APOLLO_LAKE;
 		}
@@ -967,6 +974,7 @@ static enum ich_chipset guess_ich_chipset(const struct ich_desc_content *const c
 	switch (guess) {
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_400_SERIES_COMET_POINT:
+	case CHIPSET_GEMINI_LAKE:
 		/* `freq_read` was repurposed, so can't check on it any more. */
 		return guess;
 	case CHIPSET_100_SERIES_SUNRISE_POINT:
@@ -1123,6 +1131,7 @@ int getFCBA_component_density(enum ich_chipset cs, const struct ich_descriptors
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_400_SERIES_COMET_POINT:
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		if (idx == 0) {
 			size_enc = desc->component.dens_new.comp1_density;
 		} else {
@@ -1159,6 +1168,7 @@ static uint32_t read_descriptor_reg(enum ich_chipset cs, uint8_t section, uint16
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_400_SERIES_COMET_POINT:
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		mmio_le_writel(control, spibar + PCH100_REG_FDOC);
 		return mmio_le_readl(spibar + PCH100_REG_FDOD);
 	default:

ich_descriptors.h

@@ -257,7 +257,7 @@ struct ich_desc_north_strap {
 
 struct ich_desc_south_strap {
 	union {
-		uint32_t STRPs[18]; /* current maximum: cougar point */
+		uint32_t STRPs[23]; /* current maximum: gemini lake */
 		struct { /* ich8 */
 			struct { /* STRP1 */
 				uint32_t ME_DISABLE		:1,

ichspi.c

@@ -1740,6 +1740,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_400_SERIES_COMET_POINT:
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		num_pr			= 6;	/* Includes GPR0 */
 		reg_pr0			= PCH100_REG_FPR0;
 		swseq_data.reg_ssfsc	= PCH100_REG_SSFSC;
@@ -1772,6 +1773,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
 	case CHIPSET_300_SERIES_CANNON_POINT:
 	case CHIPSET_400_SERIES_COMET_POINT:
 	case CHIPSET_APOLLO_LAKE:
+	case CHIPSET_GEMINI_LAKE:
 		num_freg = 16;
 		break;
 	default:
@@ -1868,6 +1870,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
 		case CHIPSET_300_SERIES_CANNON_POINT:
 		case CHIPSET_400_SERIES_COMET_POINT:
 		case CHIPSET_APOLLO_LAKE:
+		case CHIPSET_GEMINI_LAKE:
 			tmp = mmio_readl(spibar + PCH100_REG_DLOCK);
 			msg_pdbg("0x0c: 0x%08x (DLOCK)\n", tmp);
 			prettyprint_pch100_reg_dlock(tmp);
@@ -1943,6 +1946,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
 			case CHIPSET_300_SERIES_CANNON_POINT:
 			case CHIPSET_400_SERIES_COMET_POINT:
 			case CHIPSET_APOLLO_LAKE:
+			case CHIPSET_GEMINI_LAKE:
 			case CHIPSET_BAYTRAIL:
 				break;
 			default:
@@ -1976,6 +1980,7 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
 			case CHIPSET_300_SERIES_CANNON_POINT:
 			case CHIPSET_400_SERIES_COMET_POINT:
 			case CHIPSET_APOLLO_LAKE:
+			case CHIPSET_GEMINI_LAKE:
 				break;
 			default:
 				tmp = mmio_readl(spibar + ICH9_REG_FPB);
@@ -2012,8 +2017,10 @@ int ich_init_spi(void *spibar, enum ich_chipset ich_gen)
 			ich_spi_mode = ich_hwseq;
 		}
 
-		if (ich_spi_mode == ich_auto && ich_gen == CHIPSET_APOLLO_LAKE) {
+		if (ich_spi_mode == ich_auto &&
-			msg_pdbg("Enabling hardware sequencing by default for Apollo Lake.\n");
+		    (ich_gen == CHIPSET_APOLLO_LAKE ||
+		     ich_gen == CHIPSET_GEMINI_LAKE)) {
+			msg_pdbg("Enabling hardware sequencing by default for Apollo/Gemini Lake.\n");
 			ich_spi_mode = ich_hwseq;
 		}
 

programmer.h

@@ -672,6 +672,7 @@ enum ich_chipset {
 	CHIPSET_300_SERIES_CANNON_POINT,
 	CHIPSET_APOLLO_LAKE,
 	CHIPSET_400_SERIES_COMET_POINT,
+	CHIPSET_GEMINI_LAKE,
 };
 
 /* ichspi.c */

util/ich_descriptors_tool/ich_descriptors_tool.c

@@ -127,6 +127,7 @@ static void usage(char *argv[], const char *error)
 "\t- \"ich10\",\n"
 "\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n"
 "\t- \"apollo\" for Intel's Apollo Lake SoC.\n"
+"\t- \"gemini\" for Intel's Gemini Lake SoC.\n"
 "\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n"
 "\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n"
 "\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n"
@@ -230,6 +231,8 @@ int main(int argc, char *argv[])
 			cs = CHIPSET_400_SERIES_COMET_POINT;
 		else if (strcmp(csn, "apollo") == 0)
 			cs = CHIPSET_APOLLO_LAKE;
+		else if (strcmp(csn, "gemini") == 0)
+			cs = CHIPSET_GEMINI_LAKE;
 	}
 
 	ret = read_ich_descriptors_from_dump(buf, len, &cs, &desc);