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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 23:22:37 +02:00

Fix whitespace errors

Change-Id: Ic2d3bb9d8581a0471a8568a130f893b34dddf113
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/25380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Elyes HAOUAS 2018-03-27 12:15:09 +02:00 committed by Nico Huber
parent 3f7e341988
commit 124ef38f7a
15 changed files with 26 additions and 26 deletions

View File

@ -547,8 +547,8 @@ void w83697xx_memw_enable(uint16_t port)
} }
} else { } else {
msg_pinfo("BIOS ROM is disabled\n"); msg_pinfo("BIOS ROM is disabled\n");
} }
w836xx_ext_leave(port); w836xx_ext_leave(port);
} }
/* /*

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@ -42,7 +42,7 @@ static int buspirate_serialport_setup(char *dev)
{ {
/* 115200bps, 8 databits, no parity, 1 stopbit */ /* 115200bps, 8 databits, no parity, 1 stopbit */
sp_fd = sp_openserport(dev, BP_DEFAULTBAUD); sp_fd = sp_openserport(dev, BP_DEFAULTBAUD);
if (sp_fd == SER_INV_FD) if (sp_fd == SER_INV_FD)
return 1; return 1;
return 0; return 0;
} }

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@ -505,8 +505,8 @@ static int dediprog_spi_bulk_read(struct flashctx *flash, uint8_t *buf, unsigned
if (!transfers[i]) { if (!transfers[i]) {
msg_perr("Allocating libusb transfer %i failed: %s!\n", i, libusb_error_name(ret)); msg_perr("Allocating libusb transfer %i failed: %s!\n", i, libusb_error_name(ret));
goto err_free; goto err_free;
} }
} }
/* Now transfer requested chunks using libusb's asynchronous interface. */ /* Now transfer requested chunks using libusb's asynchronous interface. */
while (!status.error && (status.queued_idx < count)) { while (!status.error && (status.queued_idx < count)) {

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@ -3068,7 +3068,7 @@ const struct flashchip flashchips[] = {
} }
}, },
.printlock = printlock_at49f, .printlock = printlock_at49f,
.write = write_jedec_1, .write = write_jedec_1,
.read = read_memmapped, .read = read_memmapped,
.voltage = {4500, 5500}, .voltage = {4500, 5500},
}, },
@ -13833,7 +13833,7 @@ const struct flashchip flashchips[] = {
.name = "SST49LF080A", .name = "SST49LF080A",
.bustype = BUS_LPC, /* A/A Mux */ .bustype = BUS_LPC, /* A/A Mux */
.manufacture_id = SST_ID, .manufacture_id = SST_ID,
.model_id = SST_SST49LF080A, .model_id = SST_SST49LF080A,
.total_size = 1024, .total_size = 1024,
.page_size = 4096, .page_size = 4096,
.feature_bits = FEATURE_EITHER_RESET, .feature_bits = FEATURE_EITHER_RESET,

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@ -737,7 +737,7 @@ static void ich_set_bbar(uint32_t min_addr)
* may even crash. * may even crash.
*/ */
static void ich_read_data(uint8_t *data, int len, int reg0_off) static void ich_read_data(uint8_t *data, int len, int reg0_off)
{ {
int i; int i;
uint32_t temp32 = 0; uint32_t temp32 = 0;

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@ -662,7 +662,7 @@ int serprog_init(void)
} }
msg_pdbg(MSGHEADER "operation buffer size is %d\n", msg_pdbg(MSGHEADER "operation buffer size is %d\n",
sp_device_opbuf_size); sp_device_opbuf_size);
} }
if (sp_check_commandavail(S_CMD_S_PIN_STATE)) { if (sp_check_commandavail(S_CMD_S_PIN_STATE)) {
uint8_t en = 1; uint8_t en = 1;