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spi25_statusreg: support reading/writing configuration register

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One more variation of registers.

This one is read via a separate RDCR command, but written as if it's
SR2 using WRSR_EXT2.

Change-Id: I45f9afcc31f1928ef6263a749596380082963de4
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sergii Dmytruk
2022-07-24 17:11:05 +03:00
committed by Anastasia Klimchuk
parent f32f5e31d9
commit 125a328b4d
3 changed files with 33 additions and 0 deletions
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4
include/flash.h
View File

@ -161,6 +161,9 @@ enum write_granularity {
*/
#define FEATURE_SCUR (1 << 24)
/* Whether chip has configuration register (RDCR/WRSR_EXT2 commands) */
#define FEATURE_CFGR (1 << 25)
#define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)
#define UNERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00)
@ -196,6 +199,7 @@ enum flash_reg {
STATUS2,
STATUS3,
SECURITY,
CONFIG,
MAX_REGISTERS
};

5
include/spi.h
View File

@ -177,6 +177,11 @@
#define JEDEC_WRSCUR_OUTSIZE 0x01
#define JEDEC_WRSCUR_INSIZE 0x00
/* Read Configuration Register */
#define JEDEC_RDCR 0x15
#define JEDEC_RDCR_OUTSIZE 0x01
#define JEDEC_RDCR_INSIZE 0x01
/* Enter 4-byte Address Mode */
#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7