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spi25_statusreg: support reading/writing configuration register

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One more variation of registers.

This one is read via a separate RDCR command, but written as if it's
SR2 using WRSR_EXT2.

Change-Id: I45f9afcc31f1928ef6263a749596380082963de4
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sergii Dmytruk
2022-07-24 17:11:05 +03:00
committed by Anastasia Klimchuk
parent f32f5e31d9
commit 125a328b4d
3 changed files with 33 additions and 0 deletions
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24
spi25_statusreg.c
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@ -107,6 +107,23 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
*/
msg_cerr("Cannot write SECURITY: unsupported by design\n");
return 1;
case CONFIG:
/*
* This one is read via a separate command, but written as if it's SR2
* in FEATURE_WRSR_EXT2 case of WRSR command.
*/
if (feature_bits & FEATURE_CFGR) {
write_cmd[0] = JEDEC_WRSR;
if (spi_read_register(flash, STATUS1, &write_cmd[1])) {
msg_cerr("Writing CONFIG failed: failed to read SR1 for writeback.\n");
return 1;
}
write_cmd[2] = value;
write_cmd_len = 3;
break;
}
msg_cerr("Cannot write CONFIG: unsupported by chip\n");
return 1;
default:
msg_cerr("Cannot write register: unknown register\n");
return 1;
@ -209,6 +226,13 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
}
msg_cerr("Cannot read SECURITY: unsupported by chip\n");
return 1;
case CONFIG:
if (feature_bits & FEATURE_CFGR) {
read_cmd = JEDEC_RDCR;
break;
}
msg_cerr("Cannot read CONFIG: unsupported by chip\n");
return 1;
default:
msg_cerr("Cannot read register: unknown register\n");
return 1;