mirror of
https://review.coreboot.org/flashrom.git
synced 2025-04-27 07:02:34 +02:00
spi25_statusreg: support reading/writing configuration register
One more variation of registers. This one is read via a separate RDCR command, but written as if it's SR2 using WRSR_EXT2. Change-Id: I45f9afcc31f1928ef6263a749596380082963de4 Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/66211 Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Nikolai Artemiev <nartemiev@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
parent
f32f5e31d9
commit
125a328b4d
@ -161,6 +161,9 @@ enum write_granularity {
|
|||||||
*/
|
*/
|
||||||
#define FEATURE_SCUR (1 << 24)
|
#define FEATURE_SCUR (1 << 24)
|
||||||
|
|
||||||
|
/* Whether chip has configuration register (RDCR/WRSR_EXT2 commands) */
|
||||||
|
#define FEATURE_CFGR (1 << 25)
|
||||||
|
|
||||||
#define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)
|
#define ERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0x00 : 0xff)
|
||||||
#define UNERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00)
|
#define UNERASED_VALUE(flash) (((flash)->chip->feature_bits & FEATURE_ERASED_ZERO) ? 0xff : 0x00)
|
||||||
|
|
||||||
@ -196,6 +199,7 @@ enum flash_reg {
|
|||||||
STATUS2,
|
STATUS2,
|
||||||
STATUS3,
|
STATUS3,
|
||||||
SECURITY,
|
SECURITY,
|
||||||
|
CONFIG,
|
||||||
MAX_REGISTERS
|
MAX_REGISTERS
|
||||||
};
|
};
|
||||||
|
|
||||||
|
@ -177,6 +177,11 @@
|
|||||||
#define JEDEC_WRSCUR_OUTSIZE 0x01
|
#define JEDEC_WRSCUR_OUTSIZE 0x01
|
||||||
#define JEDEC_WRSCUR_INSIZE 0x00
|
#define JEDEC_WRSCUR_INSIZE 0x00
|
||||||
|
|
||||||
|
/* Read Configuration Register */
|
||||||
|
#define JEDEC_RDCR 0x15
|
||||||
|
#define JEDEC_RDCR_OUTSIZE 0x01
|
||||||
|
#define JEDEC_RDCR_INSIZE 0x01
|
||||||
|
|
||||||
/* Enter 4-byte Address Mode */
|
/* Enter 4-byte Address Mode */
|
||||||
#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7
|
#define JEDEC_ENTER_4_BYTE_ADDR_MODE 0xB7
|
||||||
|
|
||||||
|
@ -107,6 +107,23 @@ int spi_write_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
|
|||||||
*/
|
*/
|
||||||
msg_cerr("Cannot write SECURITY: unsupported by design\n");
|
msg_cerr("Cannot write SECURITY: unsupported by design\n");
|
||||||
return 1;
|
return 1;
|
||||||
|
case CONFIG:
|
||||||
|
/*
|
||||||
|
* This one is read via a separate command, but written as if it's SR2
|
||||||
|
* in FEATURE_WRSR_EXT2 case of WRSR command.
|
||||||
|
*/
|
||||||
|
if (feature_bits & FEATURE_CFGR) {
|
||||||
|
write_cmd[0] = JEDEC_WRSR;
|
||||||
|
if (spi_read_register(flash, STATUS1, &write_cmd[1])) {
|
||||||
|
msg_cerr("Writing CONFIG failed: failed to read SR1 for writeback.\n");
|
||||||
|
return 1;
|
||||||
|
}
|
||||||
|
write_cmd[2] = value;
|
||||||
|
write_cmd_len = 3;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
msg_cerr("Cannot write CONFIG: unsupported by chip\n");
|
||||||
|
return 1;
|
||||||
default:
|
default:
|
||||||
msg_cerr("Cannot write register: unknown register\n");
|
msg_cerr("Cannot write register: unknown register\n");
|
||||||
return 1;
|
return 1;
|
||||||
@ -209,6 +226,13 @@ int spi_read_register(const struct flashctx *flash, enum flash_reg reg, uint8_t
|
|||||||
}
|
}
|
||||||
msg_cerr("Cannot read SECURITY: unsupported by chip\n");
|
msg_cerr("Cannot read SECURITY: unsupported by chip\n");
|
||||||
return 1;
|
return 1;
|
||||||
|
case CONFIG:
|
||||||
|
if (feature_bits & FEATURE_CFGR) {
|
||||||
|
read_cmd = JEDEC_RDCR;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
msg_cerr("Cannot read CONFIG: unsupported by chip\n");
|
||||||
|
return 1;
|
||||||
default:
|
default:
|
||||||
msg_cerr("Cannot read register: unknown register\n");
|
msg_cerr("Cannot read register: unknown register\n");
|
||||||
return 1;
|
return 1;
|
||||||
|
Loading…
x
Reference in New Issue
Block a user