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flashchips: add support for MX77U51250F chip

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Add initial support for Macronix MX77U51250F.

Change-Id: I2c2e94f01dc63f60cf636bc6afe1f033e2a6f83c
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
This commit is contained in:
Bora Guvendik
2024-05-22 13:45:22 -07:00
parent 85b977151b
commit 131dbdc52a
2 changed files with 39 additions and 0 deletions
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38
flashchips.c
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@@ -11609,6 +11609,44 @@ const struct flashchip flashchips[] = {
.voltage = {2700, 3600},
},
{
.vendor = "Macronix",
.name = "MX77U51250F",
.bustype = BUS_SPI,
.manufacture_id = MACRONIX_ID,
.model_id = MACRONIX_MX77U51250F,
.total_size = 65536,
.page_size = 256,
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_4BA,
.tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO,
.block_erasers =
{
{
.eraseblocks = { {4 * 1024, 16384} },
.block_erase = SPI_BLOCK_ERASE_20,
}, {
.eraseblocks = { {32 * 1024, 2048} },
.block_erase = SPI_BLOCK_ERASE_52,
}, {
.eraseblocks = { {64 * 1024, 1024} },
.block_erase = SPI_BLOCK_ERASE_D8,
}, {
.eraseblocks = { {64 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_60,
}, {
.eraseblocks = { {64 * 1024 * 1024, 1} },
.block_erase = SPI_BLOCK_ERASE_C7,
}
},
.printlock = SPI_PRETTYPRINT_STATUS_REGISTER_BP3_SRWD, /* bit6 is quad enable */
.unlock = SPI_DISABLE_BLOCKPROTECT_BP3_SRWD,
.write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, /* Fast read (0x0B) supported */
.voltage = {1650, 2000},
},
/* The ST M25P05 is a bit of a problem. It has the same ID as the
* ST M25P05-A in RES mode, but supports only 128 byte writes instead
* of 256 byte writes. We rely heavily on the fact that PROBE_SPI_RES1