mirror of
https://review.coreboot.org/flashrom.git
synced 2025-07-01 22:21:16 +02:00
Random minor flashrom fixes
- Properly escape '-' chars in manpage. - Fix typo in chipset_enable.c. - Drop useless 'return' in chip_readn(). - Random other whitespace or cosmetic fixes. Corresponding to flashrom svn r636. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
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@ -393,7 +393,7 @@ static int board_asus_p5a(const char *name)
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static int board_ibm_x3455(const char *name)
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{
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/* Set GPIO lines in the Broadcom HT-1000 southbridge. */
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/* It's not a superio but it uses the same index/data port method. */
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/* It's not a Super I/O but it uses the same index/data port method. */
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sio_mask(0xcd6, 0x45, 0x20, 0x20);
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return 0;
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@ -429,7 +429,7 @@ static int board_hp_dl145_g3_enable(const char *name)
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/* Set GPIO lines in the Broadcom HT-1000 southbridge. */
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/* GPIO 0 reg from PM regs */
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/* Set GPIO 2 and 5 high, connected to flash WP# and TBL# pins. */
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/* It's not a superio but it uses the same index/data port method. */
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/* It's not a Super I/O but it uses the same index/data port method. */
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sio_mask(0xcd6, 0x44, 0x24, 0x24);
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return 0;
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@ -750,9 +750,9 @@ static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
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uint16_t rt_port = 0;
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/* Verify the chip ID. */
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OUTB(0x55, sio_port); /* enable configuration */
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OUTB(0x55, sio_port); /* Enable configuration. */
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if (sio_read(sio_port, 0x20) != chip_id) {
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fprintf(stderr, "\nERROR: SMSC super I/O not found.\n");
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fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n");
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goto out;
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}
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@ -768,7 +768,7 @@ static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
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"Super I/O runtime interface not available.\n");
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}
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out:
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OUTB(0xaa, sio_port); /* disable configuration */
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OUTB(0xaa, sio_port); /* Disable configuration. */
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return rt_port;
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}
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@ -788,18 +788,18 @@ static int board_mitac_6513wu(const char *name)
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return -1;
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}
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rt_port = smsc_find_runtime(0x4e, 0x54, 0xa);
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rt_port = smsc_find_runtime(0x4e, 0x54 /* LPC47U33x */, 0xa);
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if (rt_port == 0)
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return -1;
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/* Configure the GPIO pin. */
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val = INB(rt_port + 0x33); /* GP30 config */
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val &= ~0x87; /* output, non-inverted, GPIO, push/pull */
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val &= ~0x87; /* Output, non-inverted, GPIO, push/pull */
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OUTB(val, rt_port + 0x33);
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/* Disable write protection. */
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val = INB(rt_port + 0x4d); /* GP3 values */
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val |= 0x01; /* set GP30 high */
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val |= 0x01; /* Set GP30 high. */
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OUTB(val, rt_port + 0x4d);
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return 0;
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