openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 23:22:37 +02:00
Code Issues Releases Wiki Activity

Rename CHIP_BUSTYPE_FOO to BUS_FOO

Browse Source 
It's shorter to type, and we have less problems with the 80 column limit.

Corresponding to flashrom svn r1396.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
Carl-Daniel Hailfinger 2011-07-27 07:13:06 +00:00
parent 4deb8c6a7a
commit 1a227954f2
22 changed files with 348 additions and 348 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
atahpt.c
View File

@ -61,7 +61,7 @@ int atahpt_init(void)
reg32 |= (1 << 24); reg32 |= (1 << 24);
rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32); rpci_write_long(pcidev_dev, REG_FLASH_ACCESS, reg32);
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
if (register_shutdown(atahpt_shutdown, NULL)) if (register_shutdown(atahpt_shutdown, NULL))
return 1; return 1;

2
board_enable.c
View File

@ -425,7 +425,7 @@ int it8705f_write_enable(uint8_t port)
/* Check if at least one flash segment is enabled. */ /* Check if at least one flash segment is enabled. */
if (tmp & 0xf0) { if (tmp & 0xf0) {
/* The IT8705F will respond to LPC cycles and translate them. */ /* The IT8705F will respond to LPC cycles and translate them. */
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
/* Flash ROM I/F Writes Enable */ /* Flash ROM I/F Writes Enable */
tmp |= 0x04; tmp |= 0x04;
msg_pdbg("Enabling IT8705F flash ROM interface write.\n"); msg_pdbg("Enabling IT8705F flash ROM interface write.\n");

24
chipset_enable.c
View File

@ -210,7 +210,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
uint16_t old, new; uint16_t old, new;
uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */ uint16_t xbcs = 0x4e; /* X-Bus Chip Select register. */
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
old = pci_read_word(dev, xbcs); old = pci_read_word(dev, xbcs);
@ -297,7 +297,7 @@ static int enable_flash_ich_4e(struct pci_dev *dev, const char *name)
* FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and * FWH_DEC_EN1, but they are called FB_SEL1, FB_SEL2, FB_DEC_EN1 and
* FB_DEC_EN2. * FB_DEC_EN2.
*/ */
buses_supported = CHIP_BUSTYPE_FWH; buses_supported = BUS_FWH;
return enable_flash_ich(dev, name, 0x4e); return enable_flash_ich(dev, name, 0x4e);
} }
@ -414,7 +414,7 @@ idsel_garbage_out:
/* If we're called by enable_flash_ich_dc_spi, it will override /* If we're called by enable_flash_ich_dc_spi, it will override
* buses_supported anyway. * buses_supported anyway.
*/ */
buses_supported = CHIP_BUSTYPE_FWH; buses_supported = BUS_FWH;
return enable_flash_ich(dev, name, 0xdc); return enable_flash_ich(dev, name, 0xdc);
} }
@ -434,7 +434,7 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
if (new != old) if (new != old)
rpci_write_byte(dev, 0xd9, new); rpci_write_byte(dev, 0xd9, new);
buses_supported = CHIP_BUSTYPE_FWH; buses_supported = BUS_FWH;
return 0; return 0;
} }
@ -487,7 +487,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
* on ICH7 when the southbridge is strapped to LPC * on ICH7 when the southbridge is strapped to LPC
*/ */
buses_supported = CHIP_BUSTYPE_FWH; buses_supported = BUS_FWH;
if (ich_generation == 7) { if (ich_generation == 7) {
if(bbs == ICH_STRAP_LPC) { if(bbs == ICH_STRAP_LPC) {
/* No further SPI initialization required */ /* No further SPI initialization required */
@ -498,7 +498,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
buses_supported = 0; buses_supported = 0;
} }
/* this adds CHIP_BUSTYPE_SPI */ /* this adds BUS_SPI */
if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) { if (ich_init_spi(dev, tmp, rcrb, ich_generation) != 0) {
if (!ret) if (!ret)
ret = ERROR_NONFATAL; ret = ERROR_NONFATAL;
@ -586,7 +586,7 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
#define CS5530_ENABLE_SA2320 (1 << 2) #define CS5530_ENABLE_SA2320 (1 << 2)
#define CS5530_ENABLE_SA20 (1 << 6) #define CS5530_ENABLE_SA20 (1 << 6)
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
/* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and /* Decode 0x000E0000-0x000FFFFF (128 kB), not just 64 kB, and
* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB. * decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 kB.
* FIXME: Should we really touch the low mapping below 1 MB? Flashrom * FIXME: Should we really touch the low mapping below 1 MB? Flashrom
@ -736,7 +736,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
(prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff)); (prot & 0xfffff800) + (((prot & 0x7fc) << 8) | 0x3ff));
} }
buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; buses_supported = BUS_LPC | BUS_FWH;
ret = sb600_probe_spi(dev); ret = sb600_probe_spi(dev);
@ -822,7 +822,7 @@ static int enable_flash_osb4(struct pci_dev *dev, const char *name)
{ {
uint8_t tmp; uint8_t tmp;
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
tmp = INB(0xc06); tmp = INB(0xc06);
tmp |= 0x1; tmp |= 0x1;
@ -922,7 +922,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
switch ((val >> 5) & 0x3) { switch ((val >> 5) & 0x3) {
case 0x0: case 0x0:
ret = enable_flash_mcp55(dev, name); ret = enable_flash_mcp55(dev, name);
buses_supported = CHIP_BUSTYPE_LPC; buses_supported = BUS_LPC;
msg_pdbg("Flash bus type is LPC\n"); msg_pdbg("Flash bus type is LPC\n");
break; break;
case 0x2: case 0x2:
@ -930,7 +930,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
/* SPI is added in mcp6x_spi_init if it works. /* SPI is added in mcp6x_spi_init if it works.
* Do we really want to disable LPC in this case? * Do we really want to disable LPC in this case?
*/ */
buses_supported = CHIP_BUSTYPE_NONE; buses_supported = BUS_NONE;
msg_pdbg("Flash bus type is SPI\n"); msg_pdbg("Flash bus type is SPI\n");
msg_pinfo("SPI on this chipset is WIP. Please report any " msg_pinfo("SPI on this chipset is WIP. Please report any "
"success or failure by mailing us the verbose " "success or failure by mailing us the verbose "
@ -938,7 +938,7 @@ static int enable_flash_mcp6x_7x(struct pci_dev *dev, const char *name)
break; break;
default: default:
/* Should not happen. */ /* Should not happen. */
buses_supported = CHIP_BUSTYPE_NONE; buses_supported = BUS_NONE;
msg_pdbg("Flash bus type is unknown (none)\n"); msg_pdbg("Flash bus type is unknown (none)\n");
msg_pinfo("Something went wrong with bus type detection.\n"); msg_pinfo("Something went wrong with bus type detection.\n");
goto out_msg; goto out_msg;

2
drkaiser.c
View File

@ -64,7 +64,7 @@ int drkaiser_init(void)
drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory", drkaiser_bar = physmap("Dr. Kaiser PC-Waechter flash memory",
addr, DRKAISER_MEMMAP_SIZE); addr, DRKAISER_MEMMAP_SIZE);
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
if (register_shutdown(drkaiser_shutdown, NULL)) if (register_shutdown(drkaiser_shutdown, NULL))
return 1; return 1;

10
dummyflasher.c
View File

@ -107,24 +107,24 @@ int dummy_init(void)
/* Convert the parameters to lowercase. */ /* Convert the parameters to lowercase. */
tolower_string(bustext); tolower_string(bustext);
buses_supported = CHIP_BUSTYPE_NONE; buses_supported = BUS_NONE;
if (strstr(bustext, "parallel")) { if (strstr(bustext, "parallel")) {
buses_supported |= CHIP_BUSTYPE_PARALLEL; buses_supported |= BUS_PARALLEL;
msg_pdbg("Enabling support for %s flash.\n", "parallel"); msg_pdbg("Enabling support for %s flash.\n", "parallel");
} }
if (strstr(bustext, "lpc")) { if (strstr(bustext, "lpc")) {
buses_supported |= CHIP_BUSTYPE_LPC; buses_supported |= BUS_LPC;
msg_pdbg("Enabling support for %s flash.\n", "LPC"); msg_pdbg("Enabling support for %s flash.\n", "LPC");
} }
if (strstr(bustext, "fwh")) { if (strstr(bustext, "fwh")) {
buses_supported |= CHIP_BUSTYPE_FWH; buses_supported |= BUS_FWH;
msg_pdbg("Enabling support for %s flash.\n", "FWH"); msg_pdbg("Enabling support for %s flash.\n", "FWH");
} }
if (strstr(bustext, "spi")) { if (strstr(bustext, "spi")) {
register_spi_programmer(&spi_programmer_dummyflasher); register_spi_programmer(&spi_programmer_dummyflasher);
msg_pdbg("Enabling support for %s flash.\n", "SPI"); msg_pdbg("Enabling support for %s flash.\n", "SPI");
} }
if (buses_supported == CHIP_BUSTYPE_NONE) if (buses_supported == BUS_NONE)
msg_pdbg("Support for all flash bus types disabled.\n"); msg_pdbg("Support for all flash bus types disabled.\n");
free(bustext); free(bustext);

14
flash.h
View File

@ -57,13 +57,13 @@ void programmer_delay(int usecs);
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
enum chipbustype { enum chipbustype {
CHIP_BUSTYPE_NONE = 0, BUS_NONE = 0,
CHIP_BUSTYPE_PARALLEL = 1 << 0, BUS_PARALLEL = 1 << 0,
CHIP_BUSTYPE_LPC = 1 << 1, BUS_LPC = 1 << 1,
CHIP_BUSTYPE_FWH = 1 << 2, BUS_FWH = 1 << 2,
CHIP_BUSTYPE_SPI = 1 << 3, BUS_SPI = 1 << 3,
CHIP_BUSTYPE_NONSPI = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH, BUS_NONSPI = BUS_PARALLEL | BUS_LPC | BUS_FWH,
CHIP_BUSTYPE_UNKNOWN = CHIP_BUSTYPE_PARALLEL | CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI, BUS_UNKNOWN = BUS_PARALLEL | BUS_LPC | BUS_FWH | BUS_SPI,
}; };
/* /*

590
flashchips.c
View File

File diff suppressed because it is too large Load Diff

10
flashrom.c
View File

@ -505,7 +505,7 @@ int programmer_init(char *param)
.fwh = 0xffffffff, .fwh = 0xffffffff,
.spi = 0xffffffff .spi = 0xffffffff
}; };
buses_supported = CHIP_BUSTYPE_NONE; buses_supported = BUS_NONE;
/* Default to top aligned flash at 4 GB. */ /* Default to top aligned flash at 4 GB. */
flashbase = 0; flashbase = 0;
/* Registering shutdown functions is now allowed. */ /* Registering shutdown functions is now allowed. */
@ -1080,7 +1080,7 @@ int generate_testpattern(uint8_t *buf, uint32_t size, int variant)
int check_max_decode(enum chipbustype buses, uint32_t size) int check_max_decode(enum chipbustype buses, uint32_t size)
{ {
int limitexceeded = 0; int limitexceeded = 0;
if ((buses & CHIP_BUSTYPE_PARALLEL) && if ((buses & BUS_PARALLEL) &&
(max_rom_decode.parallel < size)) { (max_rom_decode.parallel < size)) {
limitexceeded++; limitexceeded++;
msg_pdbg("Chip size %u kB is bigger than supported " msg_pdbg("Chip size %u kB is bigger than supported "
@ -1089,7 +1089,7 @@ int check_max_decode(enum chipbustype buses, uint32_t size)
"probe/read/erase/write may fail. ", size / 1024, "probe/read/erase/write may fail. ", size / 1024,
max_rom_decode.parallel / 1024, "Parallel"); max_rom_decode.parallel / 1024, "Parallel");
} }
if ((buses & CHIP_BUSTYPE_LPC) && (max_rom_decode.lpc < size)) { if ((buses & BUS_LPC) && (max_rom_decode.lpc < size)) {
limitexceeded++; limitexceeded++;
msg_pdbg("Chip size %u kB is bigger than supported " msg_pdbg("Chip size %u kB is bigger than supported "
"size %u kB of chipset/board/programmer " "size %u kB of chipset/board/programmer "
@ -1097,7 +1097,7 @@ int check_max_decode(enum chipbustype buses, uint32_t size)
"probe/read/erase/write may fail. ", size / 1024, "probe/read/erase/write may fail. ", size / 1024,
max_rom_decode.lpc / 1024, "LPC"); max_rom_decode.lpc / 1024, "LPC");
} }
if ((buses & CHIP_BUSTYPE_FWH) && (max_rom_decode.fwh < size)) { if ((buses & BUS_FWH) && (max_rom_decode.fwh < size)) {
limitexceeded++; limitexceeded++;
msg_pdbg("Chip size %u kB is bigger than supported " msg_pdbg("Chip size %u kB is bigger than supported "
"size %u kB of chipset/board/programmer " "size %u kB of chipset/board/programmer "
@ -1105,7 +1105,7 @@ int check_max_decode(enum chipbustype buses, uint32_t size)
"probe/read/erase/write may fail. ", size / 1024, "probe/read/erase/write may fail. ", size / 1024,
max_rom_decode.fwh / 1024, "FWH"); max_rom_decode.fwh / 1024, "FWH");
} }
if ((buses & CHIP_BUSTYPE_SPI) && (max_rom_decode.spi < size)) { if ((buses & BUS_SPI) && (max_rom_decode.spi < size)) {
limitexceeded++; limitexceeded++;
msg_pdbg("Chip size %u kB is bigger than supported " msg_pdbg("Chip size %u kB is bigger than supported "
"size %u kB of chipset/board/programmer " "size %u kB of chipset/board/programmer "

2
gfxnvidia.c
View File

@ -94,7 +94,7 @@ int gfxnvidia_init(void)
reg32 &= ~(1 << 0); reg32 &= ~(1 << 0);
rpci_write_long(pcidev_dev, 0x50, reg32); rpci_write_long(pcidev_dev, 0x50, reg32);
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
/* Write/erase doesn't work. */ /* Write/erase doesn't work. */
programmer_may_write = 0; programmer_may_write = 0;

2
ichspi.c
View File

@ -1381,7 +1381,7 @@ int via_init_spi(struct pci_dev *dev)
ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70); ich_spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
/* Not sure if it speaks all these bus protocols. */ /* Not sure if it speaks all these bus protocols. */
buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH; buses_supported = BUS_LPC | BUS_FWH;
register_spi_programmer(&spi_programmer_via); register_spi_programmer(&spi_programmer_via);
msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0)); msg_pdbg("0x00: 0x%04x (SPIS)\n", mmio_readw(ich_spibar + 0));

2
internal.c
View File

@ -190,7 +190,7 @@ int internal_init(void)
/* Default to Parallel/LPC/FWH flash devices. If a known host controller /* Default to Parallel/LPC/FWH flash devices. If a known host controller
* is found, the init routine sets the buses_supported bitfield. * is found, the init routine sets the buses_supported bitfield.
*/ */
buses_supported = CHIP_BUSTYPE_NONSPI; buses_supported = BUS_NONSPI;
/* Initialize PCI access for flash enables */ /* Initialize PCI access for flash enables */
pacc = pci_alloc(); /* Get the pci_access structure */ pacc = pci_alloc(); /* Get the pci_access structure */

4
it85spi.c
View File

@ -293,7 +293,7 @@ int it85xx_spi_init(struct superio s)
{ {
int ret; int ret;
if (!(buses_supported & CHIP_BUSTYPE_FWH)) { if (!(buses_supported & BUS_FWH)) {
msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__); msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__);
return 1; return 1;
} }
@ -302,7 +302,7 @@ int it85xx_spi_init(struct superio s)
if (!ret) { if (!ret) {
msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__, msg_pdbg("%s():%d buses_supported=0x%x\n", __func__, __LINE__,
buses_supported); buses_supported);
if (buses_supported & CHIP_BUSTYPE_FWH) if (buses_supported & BUS_FWH)
msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n"); msg_pdbg("Overriding chipset SPI with IT85 FWH|SPI.\n");
/* Really leave FWH enabled? */ /* Really leave FWH enabled? */
/* Set this as spi controller. */ /* Set this as spi controller. */

2
it87spi.c
View File

@ -193,7 +193,7 @@ static uint16_t it87spi_probe(uint16_t port)
free(portpos); free(portpos);
exit_conf_mode_ite(port); exit_conf_mode_ite(port);
it8716f_flashport = flashport; it8716f_flashport = flashport;
if (buses_supported & CHIP_BUSTYPE_SPI) if (buses_supported & BUS_SPI)
msg_pdbg("Overriding chipset SPI with IT87 SPI.\n"); msg_pdbg("Overriding chipset SPI with IT87 SPI.\n");
/* FIXME: Add the SPI bus or replace the other buses with it? */ /* FIXME: Add the SPI bus or replace the other buses with it? */
register_spi_programmer(&spi_programmer_it87xx); register_spi_programmer(&spi_programmer_it87xx);

2
nic3com.c
View File

@ -96,7 +96,7 @@ int nic3com_init(void)
*/ */
OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS); OUTW(SELECT_REG_WINDOW + 0, io_base_addr + INT_STATUS);
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
max_rom_decode.parallel = 128 * 1024; max_rom_decode.parallel = 128 * 1024;
if (register_shutdown(nic3com_shutdown, NULL)) if (register_shutdown(nic3com_shutdown, NULL))

2
nicintel.c
View File

@ -93,7 +93,7 @@ int nicintel_init(void)
*/ */
pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR); pci_rmmio_writew(0x0001, nicintel_control_bar + CSR_FCR);
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE; max_rom_decode.parallel = NICINTEL_MEMMAP_SIZE;

2
nicnatsemi.c
View File

@ -48,7 +48,7 @@ int nicnatsemi_init(void)
io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi); io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_natsemi);
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
/* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15 /* The datasheet shows address lines MA0-MA16 in one place and MA0-MA15
* in another. My NIC has MA16 connected to A16 on the boot ROM socket * in another. My NIC has MA16 connected to A16 on the boot ROM socket

2
nicrealtek.c
View File

@ -50,7 +50,7 @@ int nicrealtek_init(void)
io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek); io_base_addr = pcidev_init(PCI_BASE_ADDRESS_0, nics_realtek);
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
if (register_shutdown(nicrealtek_shutdown, NULL)) if (register_shutdown(nicrealtek_shutdown, NULL))
return 1; return 1;

14
print.c
View File

@ -33,24 +33,24 @@
char *flashbuses_to_text(enum chipbustype bustype) char *flashbuses_to_text(enum chipbustype bustype)
{ {
char *ret = calloc(1, 1); char *ret = calloc(1, 1);
if (bustype == CHIP_BUSTYPE_UNKNOWN) { if (bustype == BUS_UNKNOWN) {
ret = strcat_realloc(ret, "Unknown, "); ret = strcat_realloc(ret, "Unknown, ");
/* /*
* FIXME: Once all chipsets and flash chips have been updated, NONSPI * FIXME: Once all chipsets and flash chips have been updated, NONSPI
* will cease to exist and should be eliminated here as well. * will cease to exist and should be eliminated here as well.
*/ */
} else if (bustype == CHIP_BUSTYPE_NONSPI) { } else if (bustype == BUS_NONSPI) {
ret = strcat_realloc(ret, "Non-SPI, "); ret = strcat_realloc(ret, "Non-SPI, ");
} else { } else {
if (bustype & CHIP_BUSTYPE_PARALLEL) if (bustype & BUS_PARALLEL)
ret = strcat_realloc(ret, "Parallel, "); ret = strcat_realloc(ret, "Parallel, ");
if (bustype & CHIP_BUSTYPE_LPC) if (bustype & BUS_LPC)
ret = strcat_realloc(ret, "LPC, "); ret = strcat_realloc(ret, "LPC, ");
if (bustype & CHIP_BUSTYPE_FWH) if (bustype & BUS_FWH)
ret = strcat_realloc(ret, "FWH, "); ret = strcat_realloc(ret, "FWH, ");
if (bustype & CHIP_BUSTYPE_SPI) if (bustype & BUS_SPI)
ret = strcat_realloc(ret, "SPI, "); ret = strcat_realloc(ret, "SPI, ");
if (bustype == CHIP_BUSTYPE_NONE) if (bustype == BUS_NONE)
ret = strcat_realloc(ret, "None, "); ret = strcat_realloc(ret, "None, ");
} }
/* Kill last comma. */ /* Kill last comma. */

2
satamv.c
View File

@ -137,7 +137,7 @@ int satamv_init(void)
mv_iobar = tmp & 0xffff; mv_iobar = tmp & 0xffff;
msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar); msg_pspew("Activating I/O BAR at 0x%04x\n", mv_iobar);
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
/* 512 kByte with two 8-bit latches, and /* 512 kByte with two 8-bit latches, and
* 4 MByte with additional 3-bit latch. */ * 4 MByte with additional 3-bit latch. */

2
satasii.c
View File

@ -76,7 +76,7 @@ int satasii_init(void)
if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26)))) if ((id != 0x0680) && (!(pci_mmio_readl(sii_bar) & (1 << 26))))
msg_pinfo("Warning: Flash seems unconnected.\n"); msg_pinfo("Warning: Flash seems unconnected.\n");
buses_supported = CHIP_BUSTYPE_PARALLEL; buses_supported = BUS_PARALLEL;
if (register_shutdown(satasii_shutdown, NULL)) if (register_shutdown(satasii_shutdown, NULL))
return 1; return 1;

2
serprog.c
View File

@ -462,7 +462,7 @@ int serprog_init(void)
if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) { if (sp_docommand(S_CMD_Q_BUSTYPE, 0, NULL, 1, &c)) {
msg_perr("Warning: NAK to query supported buses\n"); msg_perr("Warning: NAK to query supported buses\n");
c = CHIP_BUSTYPE_NONSPI; /* A reasonable default for now. */ c = BUS_NONSPI; /* A reasonable default for now. */
} }
buses_supported = c; buses_supported = c;

2
spi.c
View File

@ -195,5 +195,5 @@ uint32_t spi_get_valid_read_addr(void)
void register_spi_programmer(const struct spi_programmer *pgm) void register_spi_programmer(const struct spi_programmer *pgm)
{ {
spi_programmer = pgm; spi_programmer = pgm;
buses_supported |= CHIP_BUSTYPE_SPI; buses_supported |= BUS_SPI;
} }