mirror of
https://review.coreboot.org/flashrom.git
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it85spi: EOL support
This code was originally introduced by ITE for now exceedingly old Chromebooks. The code has had very little attention to maintain it, unlikely tested for a long time and now seems to be just a technical burden to the flashrom project. If someone is later interested it could be resurrected for reference from git history. However, it needs quite a bit of work to bring it back into maintainable order. BUG=b:156143896,b:170689483 TEST=tree builds under meson+make and unit tests pass. Change-Id: I5e8cafd73db837941c518f0e2d72d8192274fd79 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/flashrom/+/65378 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Anastasia Klimchuk <aklm@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Edward O'Callaghan
Edward O'Callaghan
parent
1bb5ddde60
commit
1cea47eac2
2
Makefile
2
Makefile
@ -574,7 +574,7 @@ ifeq ($(ARCH), x86)
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ifeq ($(CONFIG_INTERNAL) $(CONFIG_INTERNAL_X86), yes yes)
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ifeq ($(CONFIG_INTERNAL) $(CONFIG_INTERNAL_X86), yes yes)
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FEATURE_FLAGS += -D'CONFIG_INTERNAL=1'
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FEATURE_FLAGS += -D'CONFIG_INTERNAL=1'
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PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o \
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PROGRAMMER_OBJS += processor_enable.o chipset_enable.o board_enable.o cbtable.o \
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internal.o it87spi.o it85spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o \
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internal.o it87spi.o sb600spi.o amd_imc.o wbsio_spi.o mcp6x_spi.o \
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ichspi.o dmi.o
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ichspi.o dmi.o
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endif
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endif
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else
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else
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@ -365,9 +365,6 @@ int via_init_spi(uint32_t mmio_base);
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/* amd_imc.c */
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/* amd_imc.c */
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int amd_imc_shutdown(struct pci_dev *dev);
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int amd_imc_shutdown(struct pci_dev *dev);
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/* it85spi.c */
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int it85xx_spi_init(struct superio s);
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/* it87spi.c */
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/* it87spi.c */
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void enter_conf_mode_ite(uint16_t port);
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void enter_conf_mode_ite(uint16_t port);
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void exit_conf_mode_ite(uint16_t port);
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void exit_conf_mode_ite(uint16_t port);
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364
it85spi.c
364
it85spi.c
@ -1,364 +0,0 @@
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/*
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* This file is part of the flashrom project.
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*
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* Copyright (C) 2007, 2008, 2009 Carl-Daniel Hailfinger
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* Copyright (C) 2008 Ronald Hoogenboom <ronald@zonnet.nl>
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* Copyright (C) 2008 coresystems GmbH
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* Copyright (C) 2010 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Contains the ITE IT85* SPI specific routines
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*/
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#include <string.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include "flash.h"
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#include "spi.h"
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#include "programmer.h"
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#include "hwaccess_x86_io.h"
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#include "hwaccess_physmap.h"
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#define MAX_TIMEOUT 100000
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#define MAX_TRY 5
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/* Constants for I/O ports */
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#define ITE_SUPERIO_PORT1 0x2e
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#define ITE_SUPERIO_PORT2 0x4e
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/* Legacy I/O */
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#define LEGACY_KBC_PORT_DATA 0x60
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#define LEGACY_KBC_PORT_CMD 0x64
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/* Constants for Logical Device registers */
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#define LDNSEL 0x07
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/* These are standard Super I/O 16-bit base address registers */
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#define SHM_IO_BAR0 0x60 /* big-endian, this is high bits */
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#define SHM_IO_BAR1 0x61
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/* The 8042 keyboard controller uses an input buffer and an output buffer to
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* communicate with the host CPU. Both buffers are 1-byte depth. That means
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* IBF is set to 1 when the host CPU sends a command to the input buffer
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* of the EC. IBF is cleared to 0 once the command is read by the EC.
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*/
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#define KB_IBF (1 << 1) /* Input Buffer Full */
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#define KB_OBF (1 << 0) /* Output Buffer Full */
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/* IT8502 supports two access modes:
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* LPC_MEMORY: through the memory window in 0xFFFFFxxx (follow mode)
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* LPC_IO: through I/O port (so called indirect memory)
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*/
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#undef LPC_MEMORY
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#define LPC_IO
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#ifdef LPC_IO
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/* macro to fill in indirect-access registers. */
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#define INDIRECT_A0(base, value) OUTB(value, (base) + 0) /* little-endian */
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#define INDIRECT_A1(base, value) OUTB(value, (base) + 1)
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#define INDIRECT_A2(base, value) OUTB(value, (base) + 2)
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#define INDIRECT_A3(base, value) OUTB(value, (base) + 3)
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#define INDIRECT_READ(base) INB((base) + 4)
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#define INDIRECT_WRITE(base, value) OUTB(value, (base) + 4)
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#endif /* LPC_IO */
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struct it85spi_data {
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#ifdef LPC_IO
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unsigned int shm_io_base;
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#endif
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unsigned char *ce_high, *ce_low;
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int it85xx_scratch_rom_reenter;
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};
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/* This function will poll the keyboard status register until either
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* an expected value shows up, or the timeout is reached.
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* timeout is in usec.
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*
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* Returns: 0 -- the expected value showed up.
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* 1 -- timeout.
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*/
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static int wait_for(const unsigned int mask, const unsigned int expected_value,
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const int timeout, const char * error_message,
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const char * function_name, const int lineno)
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{
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int time_passed;
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for (time_passed = 0;; ++time_passed) {
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if ((INB(LEGACY_KBC_PORT_CMD) & mask) == expected_value)
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return 0;
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if (time_passed >= timeout)
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break;
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programmer_delay(1);
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}
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if (error_message)
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msg_perr("%s():%d %s", function_name, lineno, error_message);
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return 1;
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}
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/* IT8502 employs a scratch RAM when flash is being updated. Call the following
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* two functions before/after flash erase/program. */
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static void it85xx_enter_scratch_rom(struct it85spi_data *data)
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{
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int ret, tries;
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msg_pdbg("%s():%d was called ...\n", __func__, __LINE__);
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if (data->it85xx_scratch_rom_reenter > 0)
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return;
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#if 0
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/* FIXME: this a workaround for the bug that SMBus signal would
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* interfere the EC firmware update. Should be removed if
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* we find out the root cause. */
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ret = system("stop powerd >&2");
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if (ret)
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msg_perr("Cannot stop powerd.\n");
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#endif
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for (tries = 0; tries < MAX_TRY; ++tries) {
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/* Wait until IBF (input buffer) is not full. */
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if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
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"* timeout at waiting for IBF==0.\n",
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__func__, __LINE__))
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continue;
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/* Copy EC firmware to SRAM. */
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OUTB(0xb4, LEGACY_KBC_PORT_CMD);
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/* Confirm EC has taken away the command. */
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if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
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"* timeout at taking command.\n",
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__func__, __LINE__))
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continue;
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/* Waiting for OBF (output buffer) has data.
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* Note sometimes the replied command might be stolen by kernel
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* ISR so that it is okay as long as the command is 0xFA. */
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if (wait_for(KB_OBF, KB_OBF, MAX_TIMEOUT, NULL, NULL, 0))
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msg_pdbg("%s():%d * timeout at waiting for OBF.\n",
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__func__, __LINE__);
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if ((ret = INB(LEGACY_KBC_PORT_DATA)) == 0xFA) {
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break;
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} else {
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msg_perr("%s():%d * not run on SRAM ret=%d\n",
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__func__, __LINE__, ret);
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continue;
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}
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}
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if (tries < MAX_TRY) {
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/* EC already runs on SRAM */
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data->it85xx_scratch_rom_reenter++;
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msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__);
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} else {
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msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__);
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}
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}
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static void it85xx_exit_scratch_rom(struct it85spi_data *data)
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{
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#if 0
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int ret;
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#endif
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int tries;
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msg_pdbg("%s():%d was called ...\n", __func__, __LINE__);
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if (data->it85xx_scratch_rom_reenter <= 0)
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return;
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for (tries = 0; tries < MAX_TRY; ++tries) {
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/* Wait until IBF (input buffer) is not full. */
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if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
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"* timeout at waiting for IBF==0.\n",
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__func__, __LINE__))
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continue;
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/* Exit SRAM. Run on flash. */
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OUTB(0xFE, LEGACY_KBC_PORT_CMD);
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/* Confirm EC has taken away the command. */
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if (wait_for(KB_IBF, 0, MAX_TIMEOUT,
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"* timeout at taking command.\n",
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__func__, __LINE__)) {
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/* We cannot ensure if EC has exited update mode.
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* If EC is in normal mode already, a further 0xFE
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* command will reboot system. So, exit loop here. */
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tries = MAX_TRY;
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break;
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}
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break;
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}
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if (tries < MAX_TRY) {
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data->it85xx_scratch_rom_reenter = 0;
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msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__);
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} else {
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msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__);
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}
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#if 0
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/* FIXME: this a workaround for the bug that SMBus signal would
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* interfere the EC firmware update. Should be removed if
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* we find out the root cause. */
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ret = system("start powerd >&2");
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if (ret)
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msg_perr("Cannot start powerd again.\n");
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#endif
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}
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static int it85xx_shutdown(void *data)
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{
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msg_pdbg("%s():%d\n", __func__, __LINE__);
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it85xx_exit_scratch_rom(data);
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free(data);
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return 0; /* FIXME: Should probably return something meaningful */
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}
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/* According to ITE 8502 document, the procedure to follow mode is following:
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* 1. write 0x00 to LPC/FWH address 0xffff_fexxh (drive CE# high)
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* 2. write data to LPC/FWH address 0xffff_fdxxh (drive CE# low and MOSI
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* with data)
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* 3. read date from LPC/FWH address 0xffff_fdxxh (drive CE# low and get
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* data from MISO)
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*/
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static int it85xx_spi_send_command(const struct flashctx *flash,
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unsigned int writecnt, unsigned int readcnt,
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const unsigned char *writearr,
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unsigned char *readarr)
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{
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unsigned int i;
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struct it85spi_data *data = flash->mst->spi.data;
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it85xx_enter_scratch_rom(data);
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/*
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* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the
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* temporary flash state may halt the EC.
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*/
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#ifdef LPC_IO
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INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff);
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INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/
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INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_low) >> 8) & 0xff);
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#endif
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#ifdef LPC_MEMORY
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mmio_writeb(0, data->ce_high);
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#endif
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for (i = 0; i < writecnt; ++i) {
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#ifdef LPC_IO
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INDIRECT_WRITE(data->shm_io_base, writearr[i]);
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#endif
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#ifdef LPC_MEMORY
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mmio_writeb(writearr[i], data->ce_low);
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#endif
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}
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for (i = 0; i < readcnt; ++i) {
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#ifdef LPC_IO
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readarr[i] = INDIRECT_READ(data->shm_io_base);
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#endif
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#ifdef LPC_MEMORY
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readarr[i] = mmio_readb(data->ce_low);
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#endif
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}
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#ifdef LPC_IO
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INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff);
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INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/
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#endif
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#ifdef LPC_MEMORY
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mmio_writeb(0, data->ce_high);
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#endif
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return 0;
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}
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static const struct spi_master spi_master_it85xx = {
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.max_data_read = 64,
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.max_data_write = 64,
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.command = it85xx_spi_send_command,
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.multicommand = default_spi_send_multicommand,
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.read = default_spi_read,
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.write_256 = default_spi_write_256,
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.write_aai = default_spi_write_aai,
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.shutdown = it85xx_shutdown,
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};
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int it85xx_spi_init(struct superio s)
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{
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chipaddr base;
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struct it85spi_data *data;
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unsigned int shm_io_base = 0;
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msg_pdbg("%s():%d superio.vendor=0x%02x internal_buses_supported=0x%x\n",
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__func__, __LINE__, s.vendor, internal_buses_supported);
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/* Check for FWH because IT85 listens to FWH cycles.
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* FIXME: The big question is whether FWH cycles are necessary
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* for communication even if LPC_IO is defined.
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*/
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if (!(internal_buses_supported & BUS_FWH)) {
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msg_pdbg("%s():%d buses not support FWH\n", __func__, __LINE__);
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return 1;
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}
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msg_pdbg("Registering IT85 SPI.\n");
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#ifdef LPC_IO
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/* Get LPCPNP of SHM. That's big-endian. */
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sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
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shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) +
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sio_read(s.port, SHM_IO_BAR1);
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msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__,
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shm_io_base);
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|
||||||
/* These pointers are not used directly. They will be send to EC's
|
|
||||||
* register for indirect access. */
|
|
||||||
base = 0xFFFFF000;
|
|
||||||
|
|
||||||
/* pre-set indirect-access registers since in most of cases they are
|
|
||||||
* 0xFFFFxx00. */
|
|
||||||
INDIRECT_A0(shm_io_base, base & 0xFF);
|
|
||||||
INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF);
|
|
||||||
INDIRECT_A3(shm_io_base, (base >> 24));
|
|
||||||
#endif
|
|
||||||
#ifdef LPC_MEMORY
|
|
||||||
/* FIXME: We should block accessing that region for anything else.
|
|
||||||
* Major TODO here, and it will be a lot of work.
|
|
||||||
*/
|
|
||||||
base = physmap("it85 communication", 0xFFFFF000, 0x1000);
|
|
||||||
if (base == ERROR_PTR)
|
|
||||||
return 1;
|
|
||||||
|
|
||||||
msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
|
|
||||||
(unsigned int)base);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
data = calloc(1, sizeof(*data));
|
|
||||||
if (!data) {
|
|
||||||
msg_perr("Unable to allocate space for extra SPI master data.\n");
|
|
||||||
return SPI_GENERIC_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef LPC_IO
|
|
||||||
data->shm_io_base = shm_io_base;
|
|
||||||
#endif
|
|
||||||
data->ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */
|
|
||||||
data->ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */
|
|
||||||
|
|
||||||
/* FIXME: Really leave FWH enabled? We can't use this region
|
|
||||||
* anymore since accessing it would mess up IT85 communication.
|
|
||||||
* If we decide to disable FWH for this region, we should print
|
|
||||||
* a debug message about it.
|
|
||||||
*/
|
|
||||||
/* Set this as SPI controller. */
|
|
||||||
return register_spi_master(&spi_master_it85xx, data);
|
|
||||||
}
|
|
||||||
12
it87spi.c
12
it87spi.c
@ -449,18 +449,6 @@ int init_superio_ite(void)
|
|||||||
continue;
|
continue;
|
||||||
|
|
||||||
switch (superios[i].model) {
|
switch (superios[i].model) {
|
||||||
case 0x8500:
|
|
||||||
case 0x8502:
|
|
||||||
case 0x8510:
|
|
||||||
case 0x8511:
|
|
||||||
case 0x8512:
|
|
||||||
/* FIXME: This should be enabled, but we need a check
|
|
||||||
* for laptop whitelisting due to the amount of things
|
|
||||||
* which can go wrong if the EC firmware does not
|
|
||||||
* implement the interface we want.
|
|
||||||
*/
|
|
||||||
//it85xx_spi_init(superios[i]);
|
|
||||||
break;
|
|
||||||
case 0x8705:
|
case 0x8705:
|
||||||
ret |= it8705f_write_enable(superios[i].port);
|
ret |= it8705f_write_enable(superios[i].port);
|
||||||
break;
|
break;
|
||||||
|
|||||||
@ -271,7 +271,6 @@ if config_internal
|
|||||||
'amd_imc.c',
|
'amd_imc.c',
|
||||||
'dmi.c',
|
'dmi.c',
|
||||||
'ichspi.c',
|
'ichspi.c',
|
||||||
'it85spi.c',
|
|
||||||
'it87spi.c',
|
'it87spi.c',
|
||||||
'mcp6x_spi.c',
|
'mcp6x_spi.c',
|
||||||
'sb600spi.c',
|
'sb600spi.c',
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user