openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 22:43:17 +02:00
Code Issues Releases Wiki Activity

sbxxx: Add spispeed parameter

Browse Source 
Allow to set the SPI clock frequency on AMD chipsets with a programmer
parameter. If the parameter is given (and matches a possible value), the
SPI clock is set temporarily. Both registers are restored on programmer
shutdown.

Example: ./flashrom -p internal:spispeed="33 MHz" -V

Possible values for spispeed are "16.5 MHz", "22 MHz", "33 MHz", "66 MHz",
"100 MHZ" and "800 kHz" depending on the chipset generation.

Corresponding to flashrom svn r1795.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This commit is contained in:
Stefan Tauner
2014-05-16 21:39:48 +00:00
parent 31402ee687
commit 21071b00e3
2 changed files with 44 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

21
flashrom.8.tmpl
View File

@ -357,6 +357,27 @@ syntax. The user is responsible for supplying a suitable image or leaving out th
a layout file. This limitation might be removed in the future when we understand the details better and have
received enough feedback from users. Please report the outcome if you had to use this option to write a chip.
.sp
An optional
.B spispeed
parameter specifies the frequency of the SPI bus where applicable (i.e.\& SB600 or later with an SPI flash chip
directly attached to the chipset).
Syntax is
.sp
.B " flashrom \-p internal:spispeed=frequency"
.sp
where
.B frequency
can be
.BR "'16.5\ MHz'" ", " "'22\ MHz'" ", " "'33\ MHz'" ", " "'66\ MHz'" ", " "'100\ MHZ'" ", or " "'800\ kHz'" "."
Support of individual frequencies depends on the generation of the chipset:
.sp
* SB6xx, SB7xx, SP5xxx: from 16.5 MHz up to and including 33 MHz
.sp
* SB8xx, SB9xx, Hudson: from 16.5 MHz up to and including 66 MHz
.sp
* Yangtze (with SPI 100 engine as found in Kabini and Tamesh): all of them
.sp
The default is to use 16.5 MHz and disable Fast Reads.
.TP
.B Intel chipsets
.sp