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https://review.coreboot.org/flashrom.git
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it85spi.c: Refactor singleton states into reentrant pattern
Move global singleton states into a struct and store within the spi_master data field for the life-time of the driver. BUG=b:172876667 TEST=builds Change-Id: I389d34d62e753c012910aa5ff24a496b24a4753c Signed-off-by: Anastasia Klimchuk <aklm@chromium.org> Reviewed-on: https://review.coreboot.org/c/flashrom/+/47655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
Anastasia Klimchuk
Edward O'Callaghan
parent
c872a9fc47
commit
22f0b069bf
82
it85spi.c
82
it85spi.c
@ -73,11 +73,13 @@
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#define INDIRECT_WRITE(base, value) OUTB(value, (base) + 4)
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#endif /* LPC_IO */
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struct it85spi_data {
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#ifdef LPC_IO
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static unsigned int shm_io_base;
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unsigned int shm_io_base;
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#endif
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static unsigned char *ce_high, *ce_low;
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static int it85xx_scratch_rom_reenter = 0;
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unsigned char *ce_high, *ce_low;
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int it85xx_scratch_rom_reenter;
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};
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/* This function will poll the keyboard status register until either
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* an expected value shows up, or the timeout is reached.
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@ -106,12 +108,12 @@ static int wait_for(const unsigned int mask, const unsigned int expected_value,
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/* IT8502 employs a scratch RAM when flash is being updated. Call the following
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* two functions before/after flash erase/program. */
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static void it85xx_enter_scratch_rom(void)
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static void it85xx_enter_scratch_rom(struct it85spi_data *data)
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{
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int ret, tries;
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msg_pdbg("%s():%d was called ...\n", __func__, __LINE__);
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if (it85xx_scratch_rom_reenter > 0)
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if (data->it85xx_scratch_rom_reenter > 0)
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return;
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#if 0
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@ -156,14 +158,14 @@ static void it85xx_enter_scratch_rom(void)
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if (tries < MAX_TRY) {
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/* EC already runs on SRAM */
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it85xx_scratch_rom_reenter++;
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data->it85xx_scratch_rom_reenter++;
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msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__);
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} else {
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msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__);
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}
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}
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static void it85xx_exit_scratch_rom(void)
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static void it85xx_exit_scratch_rom(struct it85spi_data *data)
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{
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#if 0
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int ret;
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@ -171,7 +173,7 @@ static void it85xx_exit_scratch_rom(void)
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int tries;
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msg_pdbg("%s():%d was called ...\n", __func__, __LINE__);
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if (it85xx_scratch_rom_reenter <= 0)
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if (data->it85xx_scratch_rom_reenter <= 0)
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return;
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for (tries = 0; tries < MAX_TRY; ++tries) {
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@ -199,7 +201,7 @@ static void it85xx_exit_scratch_rom(void)
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}
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if (tries < MAX_TRY) {
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it85xx_scratch_rom_reenter = 0;
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data->it85xx_scratch_rom_reenter = 0;
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msg_pdbg("%s():%d * SUCCESS.\n", __func__, __LINE__);
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} else {
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msg_perr("%s():%d * Max try reached.\n", __func__, __LINE__);
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@ -218,7 +220,8 @@ static void it85xx_exit_scratch_rom(void)
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static int it85xx_shutdown(void *data)
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{
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msg_pdbg("%s():%d\n", __func__, __LINE__);
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it85xx_exit_scratch_rom();
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it85xx_exit_scratch_rom(data);
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free(data);
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return 0; /* FIXME: Should probably return something meaningful */
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}
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@ -236,48 +239,49 @@ static int it85xx_spi_send_command(const struct flashctx *flash,
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unsigned char *readarr)
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{
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unsigned int i;
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struct it85spi_data *data = flash->mst->spi.data;
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it85xx_enter_scratch_rom();
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it85xx_enter_scratch_rom(data);
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/* Exit scratch ROM ONLY when programmer shuts down. Otherwise, the
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* temporary flash state may halt the EC.
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*/
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#ifdef LPC_IO
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INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff);
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INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/
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INDIRECT_A1(shm_io_base, (((unsigned long int)ce_low) >> 8) & 0xff);
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INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff);
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INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/
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INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_low) >> 8) & 0xff);
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#endif
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#ifdef LPC_MEMORY
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mmio_writeb(0, ce_high);
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mmio_writeb(0, data->ce_high);
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#endif
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for (i = 0; i < writecnt; ++i) {
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#ifdef LPC_IO
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INDIRECT_WRITE(shm_io_base, writearr[i]);
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INDIRECT_WRITE(data->shm_io_base, writearr[i]);
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#endif
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#ifdef LPC_MEMORY
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mmio_writeb(writearr[i], ce_low);
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mmio_writeb(writearr[i], data->ce_low);
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#endif
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}
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for (i = 0; i < readcnt; ++i) {
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#ifdef LPC_IO
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readarr[i] = INDIRECT_READ(shm_io_base);
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readarr[i] = INDIRECT_READ(data->shm_io_base);
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#endif
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#ifdef LPC_MEMORY
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readarr[i] = mmio_readb(ce_low);
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readarr[i] = mmio_readb(data->ce_low);
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#endif
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}
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#ifdef LPC_IO
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INDIRECT_A1(shm_io_base, (((unsigned long int)ce_high) >> 8) & 0xff);
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INDIRECT_WRITE(shm_io_base, 0xFF); /* Write anything to this address.*/
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INDIRECT_A1(data->shm_io_base, (((unsigned long int)data->ce_high) >> 8) & 0xff);
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INDIRECT_WRITE(data->shm_io_base, 0xFF); /* Write anything to this address.*/
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#endif
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#ifdef LPC_MEMORY
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mmio_writeb(0, ce_high);
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mmio_writeb(0, data->ce_high);
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#endif
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return 0;
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}
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static const struct spi_master spi_master_it85xx = {
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static struct spi_master spi_master_it85xx = {
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.max_data_read = 64,
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.max_data_write = 64,
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.command = it85xx_spi_send_command,
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@ -291,31 +295,41 @@ static int it85xx_spi_common_init(struct superio s)
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{
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chipaddr base;
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struct it85spi_data *data = calloc(1, sizeof(struct it85spi_data));
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if (!data) {
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msg_perr("Unable to allocate space for extra SPI master data.\n");
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return SPI_GENERIC_ERROR;
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}
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spi_master_it85xx.data = data;
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msg_pdbg("%s():%d superio.vendor=0x%02x\n", __func__, __LINE__,
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s.vendor);
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if (register_shutdown(it85xx_shutdown, NULL))
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if (register_shutdown(it85xx_shutdown, data)) {
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free(data);
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return 1;
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}
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#ifdef LPC_IO
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/* Get LPCPNP of SHM. That's big-endian. */
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sio_write(s.port, LDNSEL, 0x0F); /* Set LDN to SHM (0x0F) */
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shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) +
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data->shm_io_base = (sio_read(s.port, SHM_IO_BAR0) << 8) +
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sio_read(s.port, SHM_IO_BAR1);
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msg_pdbg("%s():%d shm_io_base=0x%04x\n", __func__, __LINE__,
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shm_io_base);
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msg_pdbg("%s():%d it85spi_data->shm_io_base=0x%04x\n", __func__, __LINE__,
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data->shm_io_base);
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/* These pointers are not used directly. They will be send to EC's
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* register for indirect access. */
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base = 0xFFFFF000;
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ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */
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ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */
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data->ce_high = ((unsigned char *)base) + 0xE00; /* 0xFFFFFE00 */
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data->ce_low = ((unsigned char *)base) + 0xD00; /* 0xFFFFFD00 */
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/* pre-set indirect-access registers since in most of cases they are
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* 0xFFFFxx00. */
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INDIRECT_A0(shm_io_base, base & 0xFF);
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INDIRECT_A2(shm_io_base, (base >> 16) & 0xFF);
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INDIRECT_A3(shm_io_base, (base >> 24));
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INDIRECT_A0(data->shm_io_base, base & 0xFF);
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INDIRECT_A2(data->shm_io_base, (base >> 16) & 0xFF);
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INDIRECT_A3(data->shm_io_base, (base >> 24));
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#endif
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#ifdef LPC_MEMORY
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/* FIXME: We should block accessing that region for anything else.
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@ -327,8 +341,8 @@ static int it85xx_spi_common_init(struct superio s)
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msg_pdbg("%s():%d base=0x%08x\n", __func__, __LINE__,
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(unsigned int)base);
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ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */
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ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */
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data->ce_high = (unsigned char *)(base + 0xE00); /* 0xFFFFFE00 */
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data->ce_low = (unsigned char *)(base + 0xD00); /* 0xFFFFFD00 */
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#endif
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return 0;
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