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mirror of https://review.coreboot.org/flashrom.git synced 2025-04-27 15:12:36 +02:00

Fix typo (s/Bit/Bits/) to clarify code comment

Corresponding to flashrom svn r1135.

 
Signed-off-by: David Borg <borg.db@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
David Borg 2010-08-08 17:04:21 +00:00 committed by Uwe Hermann
parent 48ec1b17d8
commit 243ec63305

View File

@ -68,8 +68,8 @@ void nicnatsemi_chip_writeb(uint8_t val, chipaddr addr)
/* /*
* The datasheet requires 32 bit accesses to this register, but it seems * The datasheet requires 32 bit accesses to this register, but it seems
* that requirement might only apply if the register is memory mapped. * that requirement might only apply if the register is memory mapped.
* Bit 8-31 of this register are apparently don't care, and if this * Bits 8-31 of this register are apparently don't care, and if this
* register is I/O port mapped 8 bit accesses to the lowest byte of the * register is I/O port mapped, 8 bit accesses to the lowest byte of the
* register seem to work fine. Due to that, we ignore the advice in the * register seem to work fine. Due to that, we ignore the advice in the
* data sheet. * data sheet.
*/ */
@ -82,8 +82,8 @@ uint8_t nicnatsemi_chip_readb(const chipaddr addr)
/* /*
* The datasheet requires 32 bit accesses to this register, but it seems * The datasheet requires 32 bit accesses to this register, but it seems
* that requirement might only apply if the register is memory mapped. * that requirement might only apply if the register is memory mapped.
* Bit 8-31 of this register are apparently don't care, and if this * Bits 8-31 of this register are apparently don't care, and if this
* register is I/O port mapped 8 bit accesses to the lowest byte of the * register is I/O port mapped, 8 bit accesses to the lowest byte of the
* register seem to work fine. Due to that, we ignore the advice in the * register seem to work fine. Due to that, we ignore the advice in the
* data sheet. * data sheet.
*/ */