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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-01 22:21:16 +02:00

Introduce additional SPI status register helpers

- spi_prettyprint_status_register_default_welwip():
   It just prettyprints the plain hex value and the welwip bits.
 - spi_prettyprint_status_register_default_bp4():
   Prints the hex value, welwip, bp0-5 and srwd bits.
 - spi_disable_blockprotect_bp2_srwd(),
 - spi_disable_blockprotect_bp3_srwd() and
   spi_disable_blockprotect_bp4_srwd():
   Three new common block unprotection functions for the frequent
   cases where there is a status register lock bit at bit #7 and some
   block protection bits at bits #2-#4, #2-#5 and #2-#6 respectively.

Corresponding to flashrom svn r1681.

Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This commit is contained in:
Stefan Tauner
2013-06-28 21:28:27 +00:00
parent 682122bce7
commit 278ba6e967
3 changed files with 52 additions and 9 deletions

View File

@ -196,6 +196,27 @@ int spi_disable_blockprotect(struct flashctx *flash)
return spi_disable_blockprotect_generic(flash, 0x3C, 0, 0, 0xFF);
}
/* A common block protection disable that tries to unset the status register bits masked by 0x1C (BP0-2) and
* protected/locked by bit #7. Useful when bit #5 is neither a protection bit nor reserved (and hence possibly
* non-0). */
int spi_disable_blockprotect_bp2_srwd(struct flashctx *flash)
{
return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0, 0xFF);
}
/* A common block protection disable that tries to unset the status register bits masked by 0x3C (BP0-3) and
* protected/locked by bit #7. */
int spi_disable_blockprotect_bp3_srwd(struct flashctx *flash)
{
return spi_disable_blockprotect_generic(flash, 0x3C, 1 << 7, 0, 0xFF);
}
/* A common block protection disable that tries to unset the status register bits masked by 0x7C (BP0-4) and
* protected/locked by bit #7. */
int spi_disable_blockprotect_bp4_srwd(struct flashctx *flash)
{
return spi_disable_blockprotect_generic(flash, 0x7C, 1 << 7, 0, 0xFF);
}
static void spi_prettyprint_status_register_hex(uint8_t status)
{
@ -261,6 +282,16 @@ int spi_prettyprint_status_register_plain(struct flashctx *flash)
return 0;
}
/* Print the plain hex value and the welwip bits only. */
int spi_prettyprint_status_register_default_welwip(struct flashctx *flash)
{
uint8_t status = spi_read_status_register(flash);
spi_prettyprint_status_register_hex(status);
spi_prettyprint_status_register_welwip(status);
return 0;
}
/* Works for many chips of the
* AMIC A25L series
* and MX MX25L512
@ -312,6 +343,17 @@ int spi_prettyprint_status_register_default_bp3(struct flashctx *flash)
return 0;
}
int spi_prettyprint_status_register_default_bp4(struct flashctx *flash)
{
uint8_t status = spi_read_status_register(flash);
spi_prettyprint_status_register_hex(status);
spi_prettyprint_status_register_srwd(status);
spi_prettyprint_status_register_bp(status, 4);
spi_prettyprint_status_register_welwip(status);
return 0;
}
/* === Amic ===
* FIXME: spi_disable_blockprotect is incorrect but works fine for chips using
* spi_prettyprint_status_register_default_bp1 or
@ -539,11 +581,6 @@ int spi_disable_blockprotect_at25f512b(struct flashctx *flash)
return spi_disable_blockprotect_generic(flash, 0x04, 1 << 7, 1 << 4, 0xFF);
}
int spi_disable_blockprotect_at25f4096(struct flashctx *flash)
{
return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0, 0xFF);
}
int spi_disable_blockprotect_at25fs010(struct flashctx *flash)
{
return spi_disable_blockprotect_generic(flash, 0x6C, 1 << 7, 0, 0xFF);
@ -559,7 +596,7 @@ int spi_disable_blockprotect_at25fs040(struct flashctx *flash)
/* TODO: Clear P_FAIL and E_FAIL with Clear SR Fail Flags Command (30h) here? */
int spi_disable_blockprotect_s33(struct flashctx *flash)
{
return spi_disable_blockprotect_generic(flash, 0x1C, 1 << 7, 0, 0xFF);
return spi_disable_blockprotect_bp2_srwd(flash);
}
int spi_prettyprint_status_register_s33(struct flashctx *flash)