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https://review.coreboot.org/flashrom.git
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Use the maximum decode size infrastructure
- Detect max FWH size for Intel 631xESB/632xESB/3100/ICH6/ICH7/ICH8/ICH9/ICH10. - Move IDSEL override before decode size checking for the chipsets listed above or flashrom will complain based on old values. - Adjust supported flash buses for the chipsets listed above (none of them supports LPC or Parallel). - Detect max parallel size for AMD/National Semiconductor CS5530. - Adjust supported flash buses for CS5530/CS5530A. - Set board-specific max decode size for Elitegroup K7VTA3. - Set board-specific max decode size for Shuttle AK38N. Corresponding to flashrom svn r806. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
This commit is contained in:
Carl-Daniel Hailfinger
parent
c12fc71f74
commit
2a9e2455cd
@ -987,12 +987,20 @@ static int it8705f_write_enable(uint8_t port, const char *name)
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}
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/**
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* Suited for:
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* - Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
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* - Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
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* Suited for: Elitegroup K7VTA3: VIA Apollo KT266/A/333 + VIA VT8235 + ITE IT8705F
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*/
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static int it8705f_write_enable_2e(const char *name)
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static int elitegroup_k7vta3(const char *name)
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{
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max_rom_decode.parallel = 256 * 1024;
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return it8705f_write_enable(0x2e, name);
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}
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/**
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* Suited for: Shuttle AK38N: VIA KT333CF + VIA VT8235 + ITE IT8705F
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*/
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static int shuttle_ak38n(const char *name)
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{
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max_rom_decode.parallel = 256 * 1024;
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return it8705f_write_enable(0x2e, name);
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}
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@ -1233,7 +1241,7 @@ struct board_pciid_enable board_pciid_enables[] = {
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{0x10DE, 0x0030, 0x1043, 0x818a, 0x8086, 0x100E, 0x1043, 0x80EE, NULL, NULL, "ASUS", "P5ND2-SLI Deluxe", nvidia_mcp_gpio10_raise},
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{0x1106, 0x3149, 0x1565, 0x3206, 0x1106, 0x3344, 0x1565, 0x1202, NULL, NULL, "Biostar", "P4M80-M4", it8705_rom_write_enable},
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{0x8086, 0x3590, 0x1028, 0x016c, 0x1000, 0x0030, 0x1028, 0x016c, NULL, NULL, "Dell", "PowerEdge 1850", intel_ich_gpio23_raise},
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{0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", it8705f_write_enable_2e},
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{0x1106, 0x3038, 0x1019, 0x0996, 0x1106, 0x3177, 0x1019, 0x0996, NULL, NULL, "Elitegroup", "K7VTA3", elitegroup_k7vta3},
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{0x1106, 0x3177, 0x1106, 0x3177, 0x1106, 0x3059, 0x1695, 0x3005, NULL, NULL, "EPoX", "EP-8K5A2", w836xx_memw_enable_2e},
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{0x10EC, 0x8139, 0x1695, 0x9001, 0x11C1, 0x5811, 0x1695, 0x9015, NULL, NULL, "EPoX", "EP-8RDA3+", nvidia_mcp_gpio31_raise},
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{0x8086, 0x7110, 0, 0, 0x8086, 0x7190, 0, 0, "epox", "ep-bx3", "EPoX", "EP-BX3", board_epox_ep_bx3},
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@ -1257,7 +1265,7 @@ struct board_pciid_enable board_pciid_enables[] = {
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{0x8086, 0x2658, 0x1462, 0x7046, 0x1106, 0x3044, 0x1462, 0x046d, NULL, NULL, "MSI", "MS-7046", intel_ich_gpio19_raise},
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{0x10DE, 0x005E, 0x1462, 0x7135, 0x10DE, 0x0050, 0x1462, 0x7135, "msi", "k8n-neo3", "MSI", "MS-7135 (K8N Neo3)", w83627thf_gpio4_4_raise_4e},
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{0x1106, 0x3099, 0, 0, 0x1106, 0x3074, 0, 0, "shuttle", "ak31", "Shuttle", "AK31", w836xx_memw_enable_2e},
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{0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", it8705f_write_enable_2e},
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{0x1106, 0x3104, 0x1297, 0xa238, 0x1106, 0x3059, 0x1297, 0xc063, NULL, NULL, "Shuttle", "AK38N", shuttle_ak38n},
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{0x10DE, 0x0050, 0x1297, 0x5036, 0x1412, 0x1724, 0x1297, 0x5036, NULL, NULL, "Shuttle", "FN25", board_shuttle_fn25},
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{0x1106, 0x3038, 0x0925, 0x1234, 0x1106, 0x3058, 0x15DD, 0x7609, NULL, NULL, "Soyo", "SY-7VCA", board_soyo_sy_7vca},
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{0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498, NULL, NULL, "Tyan", "S2498 (Tomcat K7M)", board_asus_a7v8x_mx},
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137
chipset_enable.c
137
chipset_enable.c
@ -4,6 +4,7 @@
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* Copyright (C) 2000 Silicon Integrated System Corporation
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* Copyright (C) 2005-2009 coresystems GmbH
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* Copyright (C) 2006 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2007,2008,2009 Carl-Daniel Hailfinger
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -301,34 +302,10 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
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uint32_t fwh_conf;
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int i;
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char *idsel = NULL;
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/* Ignore all legacy ranges below 1 MB. */
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/* FWH_SEL1 */
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fwh_conf = pci_read_long(dev, 0xd0);
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for (i = 7; i >= 0; i--)
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printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
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(0x1ff8 + i) * 0x80000,
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(0x1ff0 + i) * 0x80000,
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(fwh_conf >> (i * 4)) & 0xf);
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/* FWH_SEL2 */
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fwh_conf = pci_read_word(dev, 0xd4);
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for (i = 3; i >= 0; i--)
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printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
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(0xff4 + i) * 0x100000,
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(0xff0 + i) * 0x100000,
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(fwh_conf >> (i * 4)) & 0xf);
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/* FWH_DEC_EN1 */
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fwh_conf = pci_read_word(dev, 0xd8);
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for (i = 7; i >= 0; i--)
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printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
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(0x1ff8 + i) * 0x80000,
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(0x1ff0 + i) * 0x80000,
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(fwh_conf >> (i + 0x8)) & 0x1 ? "en" : "dis");
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for (i = 3; i >= 0; i--)
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printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
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(0xff4 + i) * 0x100000,
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(0xff0 + i) * 0x100000,
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(fwh_conf >> i) & 0x1 ? "en" : "dis");
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int tmp;
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int max_decode_fwh_idsel = 0;
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int max_decode_fwh_decode = 0;
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int contiguous = 1;
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if (programmer_param)
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idsel = strstr(programmer_param, "fwh_idsel=");
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@ -341,8 +318,76 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
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printf("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf);
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pci_write_long(dev, 0xd0, fwh_conf);
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pci_write_word(dev, 0xd4, fwh_conf);
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/* FIXME: Decode settings are not changed. */
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}
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/* Ignore all legacy ranges below 1 MB.
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* We currently only support flashing the chip which responds to
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* IDSEL=0. To support IDSEL!=0, flashbase and decode size calculations
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* have to be adjusted.
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*/
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/* FWH_SEL1 */
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fwh_conf = pci_read_long(dev, 0xd0);
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for (i = 7; i >= 0; i--) {
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tmp = (fwh_conf >> (i * 4)) & 0xf;
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printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
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(0x1ff8 + i) * 0x80000,
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(0x1ff0 + i) * 0x80000,
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tmp);
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if ((tmp == 0) && contiguous) {
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max_decode_fwh_idsel = (8 - i) * 0x80000;
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} else {
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contiguous = 0;
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}
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}
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/* FWH_SEL2 */
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fwh_conf = pci_read_word(dev, 0xd4);
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for (i = 3; i >= 0; i--) {
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tmp = (fwh_conf >> (i * 4)) & 0xf;
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printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
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(0xff4 + i) * 0x100000,
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(0xff0 + i) * 0x100000,
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tmp);
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if ((tmp == 0) && contiguous) {
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max_decode_fwh_idsel = (8 - i) * 0x100000;
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} else {
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contiguous = 0;
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}
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}
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contiguous = 1;
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/* FWH_DEC_EN1 */
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fwh_conf = pci_read_word(dev, 0xd8);
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for (i = 7; i >= 0; i--) {
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tmp = (fwh_conf >> (i + 0x8)) & 0x1;
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printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
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(0x1ff8 + i) * 0x80000,
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(0x1ff0 + i) * 0x80000,
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tmp ? "en" : "dis");
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if ((tmp == 0) && contiguous) {
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max_decode_fwh_decode = (8 - i) * 0x80000;
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} else {
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contiguous = 0;
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}
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}
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for (i = 3; i >= 0; i--) {
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tmp = (fwh_conf >> i) & 0x1;
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printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
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(0xff4 + i) * 0x100000,
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(0xff0 + i) * 0x100000,
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tmp ? "en" : "dis");
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if ((tmp == 0) && contiguous) {
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max_decode_fwh_decode = (8 - i) * 0x100000;
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} else {
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contiguous = 0;
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}
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}
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max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
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printf_debug("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
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/* If we're called by enable_flash_ich_dc_spi, it will override
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* buses_supported anyway.
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*/
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buses_supported = CHIP_BUSTYPE_FWH;
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return enable_flash_ich(dev, name, 0xdc);
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}
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@ -355,6 +400,7 @@ static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
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{
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uint32_t mmio_base;
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/* Do we really need no write enable? */
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mmio_base = (pci_read_long(dev, 0xbc)) << 8;
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printf_debug("MMIO base at = 0x%x\n", mmio_base);
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spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
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@ -409,8 +455,7 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
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*/
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if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
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/* Not sure if it speaks LPC as well. */
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buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH;
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buses_supported = CHIP_BUSTYPE_FWH;
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/* No further SPI initialization required */
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return ret;
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}
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@ -422,16 +467,14 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
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spibar_offset = 0x3020;
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break;
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case 8:
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/* Not sure if it speaks LPC as well. */
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buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
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buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
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spi_controller = SPI_CONTROLLER_ICH9;
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spibar_offset = 0x3020;
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break;
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case 9:
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case 10:
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default: /* Future version might behave the same */
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/* Not sure if it speaks LPC as well. */
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buses_supported = CHIP_BUSTYPE_LPC | CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
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buses_supported = CHIP_BUSTYPE_FWH | CHIP_BUSTYPE_SPI;
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spi_controller = SPI_CONTROLLER_ICH9;
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spibar_offset = 0x3800;
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break;
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@ -612,14 +655,22 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
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#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
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#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
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#define CS5530_RESET_CONTROL_REG 0x44 /* F0 index 0x44 */
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#define CS5530_USB_SHADOW_REG 0x43 /* F0 index 0x43 */
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#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
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#define ROM_WRITE_ENABLE (1 << 1)
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#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
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#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
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#define CS5530_ISA_MASTER (1 << 7)
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#define CS5530_ENABLE_SA2320 (1 << 2)
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#define CS5530_ENABLE_SA20 (1 << 6)
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buses_supported = CHIP_BUSTYPE_PARALLEL;
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/* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
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* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
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* FIXME: Should we really touch the low mapping below 1 MB? Flashrom
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* ignores that region completely.
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* Make the configured ROM areas writable.
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*/
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reg8 = pci_read_byte(dev, ROM_AT_LOGIC_CONTROL_REG);
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@ -633,6 +684,24 @@ static int enable_flash_cs5530(struct pci_dev *dev, const char *name)
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reg8 |= BIOS_ROM_POSITIVE_DECODE;
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pci_write_byte(dev, DECODE_CONTROL_REG2, reg8);
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reg8 = pci_read_byte(dev, CS5530_RESET_CONTROL_REG);
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if (reg8 & CS5530_ISA_MASTER) {
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/* We have A0-A23 available. */
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max_rom_decode.parallel = 16 * 1024 * 1024;
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} else {
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reg8 = pci_read_byte(dev, CS5530_USB_SHADOW_REG);
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if (reg8 & CS5530_ENABLE_SA2320) {
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/* We have A0-19, A20-A23 available. */
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max_rom_decode.parallel = 16 * 1024 * 1024;
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} else if (reg8 & CS5530_ENABLE_SA20) {
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/* We have A0-19, A20 available. */
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max_rom_decode.parallel = 2 * 1024 * 1024;
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} else {
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/* A20 and above are not active. */
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max_rom_decode.parallel = 1024 * 1024;
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}
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}
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return 0;
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}
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