mirror of
https://review.coreboot.org/flashrom.git
synced 2025-07-02 06:23:18 +02:00
First attempt to clean up SPI probing and create a common construct: the flash bus
At some point the flash bus will be part of struct flashchip. Pardon me for pushing this in, but I think it is important to beware of further decay and it will improve things for other developers in the short run. Carl-Daniel, I will consider your suggestions in another patch. I want to keep things from getting too much for now. The patch includes Rudolf's VIA SPI changes though. Corresponding to flashrom svn r285 and coreboot v2 svn r3401. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Stefan Reinauer
committed by
Stefan Reinauer
Stefan Reinauer
parent
e3eb9c1d69
commit
2cb94e183b
144
chipset_enable.c
144
chipset_enable.c
@ -35,6 +35,17 @@
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#include <unistd.h>
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#include "flash.h"
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/**
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* flashrom defaults to LPC flash devices. If a known SPI controller is found
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* and the SPI strappings are set, this will be overwritten by the probing code.
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*
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* Eventually, this will become an array when multiple flash support works.
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*/
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flashbus_t flashbus = BUS_TYPE_LPC;
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void *spibar = NULL;
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static int enable_flash_ali_m1533(struct pci_dev *dev, const char *name)
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{
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uint8_t tmp;
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@ -124,7 +135,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
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* Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
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* Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
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*/
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new = old | 0x2c4;
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new = old | 0x02c4;
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if (new == old)
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return 0;
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@ -185,88 +196,131 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
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return enable_flash_ich(dev, name, 0xdc);
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}
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void *ich_spibar = NULL;
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#define ICH_STRAP_RSVD 0x00
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#define ICH_STRAP_SPI 0x01
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#define ICH_STRAP_PCI 0x02
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#define ICH_STRAP_LPC 0x03
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static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name) {
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uint32_t mmio_base;
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mmio_base = (pci_read_long(dev, 0xbc)) << 8;
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printf_debug("MMIO base at = 0x%x\n", mmio_base);
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ich_spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
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spibar = mmap(NULL, 0x70, PROT_READ | PROT_WRITE, MAP_SHARED,
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fd_mem, mmio_base);
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if (ich_spibar == MAP_FAILED) {
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if (spibar == MAP_FAILED) {
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perror("Can't mmap memory using " MEM_DEV);
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exit(1);
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}
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printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", *(uint16_t *)(ich_spibar + 0x6c));
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viaspi_detected = 1;
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printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n", *(uint16_t *)(spibar + 0x6c));
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flashbus = BUS_TYPE_VIA_SPI;
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return 0;
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}
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static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsigned long spibar)
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static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, int ich_generation)
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{
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int ret, i;
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uint8_t old, new, bbs, buc;
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uint16_t spibar_offset;
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uint32_t tmp, gcs;
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void *rcrb;
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static const char *straps_names[] = { "reserved", "SPI", "PCI", "LPC" };
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/* Enable Flash Writes */
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ret = enable_flash_ich_dc(dev, name);
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/* Read the Root Complex Base Address Register (RCBA) */
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tmp = pci_read_long(dev, 0xf0);
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/* Calculate the Root Complex Register Block address */
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tmp &= 0xffffc000;
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/* Get physical address of Root Complex Register Block */
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tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
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printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
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/* Map RCBA to virtual memory */
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rcrb = mmap(0, 0x4000, PROT_READ | PROT_WRITE, MAP_SHARED, fd_mem, (off_t)tmp);
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if (rcrb == MAP_FAILED) {
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perror("Can't mmap memory using " MEM_DEV);
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exit(1);
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}
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printf_debug("GCS address = 0x%x\n", tmp + 0x3410);
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gcs = *(volatile uint32_t *)(rcrb + 0x3410);
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printf_debug("GCS = 0x%x: ", gcs);
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printf_debug("BIOS Interface Lock-Down: %sabled, ",
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(gcs & 0x1) ? "en" : "dis");
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bbs = (gcs >> 10) & 0x3;
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printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs,
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(bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI"));
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if (bbs >= 2)
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ich7_detected = 0;
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printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
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buc = *(volatile uint8_t *)(rcrb + 0x3414);
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printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not enabled");
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/* It seems the ICH7 does not support SPI and LPC chips at the same
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* time. At least not with our current code. So we prevent searching
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* on ICH7 when the southbridge is strapped to LPC
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*/
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if (ich_generation == 7 && bbs == ICH_STRAP_LPC) {
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/* No further SPI initialization required */
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return ret;
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}
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switch (ich_generation) {
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case 7:
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flashbus = BUS_TYPE_ICH7_SPI;
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spibar_offset = 0x3020;
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break;
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case 8:
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flashbus = BUS_TYPE_ICH9_SPI;
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spibar_offset = 0x3020;
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break;
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case 9:
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default: /* Future version might behave the same */
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flashbus = BUS_TYPE_ICH9_SPI;
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spibar_offset = 0x3800;
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break;
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}
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/* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
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printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, (uint16_t)spibar);
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printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
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// Assign Virtual Address
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ich_spibar = rcrb + spibar;
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/* Assign Virtual Address */
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spibar = rcrb + spibar_offset;
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if (ich7_detected) {
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int i;
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printf_debug("0x00: 0x%04x (SPIS)\n", *(uint16_t *)(ich_spibar + 0));
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printf_debug("0x02: 0x%04x (SPIC)\n", *(uint16_t *)(ich_spibar + 2));
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printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(ich_spibar + 4));
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switch (flashbus) {
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case BUS_TYPE_ICH7_SPI:
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printf_debug("0x00: 0x%04x (SPIS)\n", *(uint16_t *)(spibar + 0));
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printf_debug("0x02: 0x%04x (SPIC)\n", *(uint16_t *)(spibar + 2));
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printf_debug("0x04: 0x%08x (SPIA)\n", *(uint32_t *)(spibar + 4));
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for (i=0; i < 8; i++) {
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int offs;
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offs = 8 + (i * 8);
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printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i);
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printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(ich_spibar + offs +4), i);
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printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs, *(uint32_t *)(spibar + offs), i);
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printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs+4, *(uint32_t *)(spibar + offs +4), i);
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}
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printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(ich_spibar + 0x50));
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printf_debug("0x54: 0x%04x (PREOP)\n", *(uint16_t *)(ich_spibar + 0x54));
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printf_debug("0x56: 0x%04x (OPTYPE)\n", *(uint16_t *)(ich_spibar + 0x56));
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printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(ich_spibar + 0x58));
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printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(ich_spibar + 0x5c));
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printf_debug("0x50: 0x%08x (BBAR)\n", *(uint32_t *)(spibar + 0x50));
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printf_debug("0x54: 0x%04x (PREOP)\n", *(uint16_t *)(spibar + 0x54));
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printf_debug("0x56: 0x%04x (OPTYPE)\n", *(uint16_t *)(spibar + 0x56));
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printf_debug("0x58: 0x%08x (OPMENU)\n", *(uint32_t *)(spibar + 0x58));
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printf_debug("0x5c: 0x%08x (OPMENU+4)\n", *(uint32_t *)(spibar + 0x5c));
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for (i=0; i < 4; i++) {
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int offs;
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offs = 0x60 + (i * 4);
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printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(ich_spibar + offs), i);
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printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs, *(uint32_t *)(spibar + offs), i);
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}
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printf_debug("\n");
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if ( (*(uint16_t *)ich_spibar) & (1 << 15)) {
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if ( (*(uint16_t *)spibar) & (1 << 15)) {
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printf("WARNING: SPI Configuration Lockdown activated.\n");
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}
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break;
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case BUS_TYPE_ICH9_SPI:
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/* TODO: Add dumping function for ICH8/ICH9, or drop the
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* whole SPIBAR dumping from chipset_enable.c - There's
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* inteltool for this task already.
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*/
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break;
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default:
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/* Nothing */
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break;
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}
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old = pci_read_byte(dev, 0xdc);
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@ -277,38 +331,30 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name, unsign
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case 1:
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case 2:
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printf_debug("prefetching %sabled, caching %sabled, ",
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(new & 0x2) ? "en" : "dis", (new & 0x1) ? "dis" : "en");
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(new & 0x2) ? "en" : "dis",
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(new & 0x1) ? "dis" : "en");
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break;
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default:
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printf_debug("invalid prefetching/caching settings, ");
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break;
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}
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return enable_flash_ich_dc(dev, name);
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}
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/* Flag for ICH7 SPI register block */
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int ich7_detected = 0;
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int viaspi_detected = 0;
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return ret;
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}
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static int enable_flash_ich7(struct pci_dev *dev, const char *name)
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{
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ich7_detected = 1;
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return enable_flash_ich_dc_spi(dev, name, 0x3020);
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return enable_flash_ich_dc_spi(dev, name, 7);
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}
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/* Flag for ICH8/ICH9 SPI register block */
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int ich9_detected = 0;
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static int enable_flash_ich8(struct pci_dev *dev, const char *name)
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{
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ich9_detected = 1;
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return enable_flash_ich_dc_spi(dev, name, 0x3020);
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return enable_flash_ich_dc_spi(dev, name, 8);
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}
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static int enable_flash_ich9(struct pci_dev *dev, const char *name)
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{
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ich9_detected = 1;
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return enable_flash_ich_dc_spi(dev, name, 0x3800);
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return enable_flash_ich_dc_spi(dev, name, 9);
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}
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static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
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