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Rework internal bus handling and laptop bail-out

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We used to bail out on any unknown laptop. However, modern systems with
SPI flashes don't suffer from the original problem. Even if a flash chip
is shared with the EC, the latter has to expect the host to send regular
JEDEC SPI commands any time.

So instead of bailing out, we limit the set of buses to probe. If we
suspect to be running on a laptop, we only allow probing of SPI and
opaque programmers. The user can still use the existing force options
to probe all buses.

This will obsolete some board-enables that could be moved to `print.c`
in follow-up commits.

Change-Id: I1dbda8cf0c10d7786106f14f0d18c3dcce35f0a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/28716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Thomas Heijligen <src@posteo.de>
This commit is contained in:
Nico Huber
2018-09-23 20:20:26 +02:00
parent ba22411335
commit 2e50cdc494
6 changed files with 500 additions and 424 deletions
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2
ichspi.c
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@ -2010,7 +2010,7 @@ int via_init_spi(uint32_t mmio_base)
/* Do we really need no write enable? Like the LPC one at D17F0 0x40 */
/* Not sure if it speaks all these bus protocols. */
internal_buses_supported = BUS_LPC | BUS_FWH;
internal_buses_supported &= BUS_LPC | BUS_FWH;
ich_generation = CHIPSET_ICH7;
register_spi_master(&spi_master_via);