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Code Issues Releases Wiki Activity

flashchips: Add write protect bits to W25Q64JW...M

Browse Source 
https://www.winbond.com/hq/support/documentation/levelOne.jsp?__locale=en&DocNo=DA00-W25Q64JW

BUG=b:245996788
BRANCH=None
TEST=None

Change-Id: Idf2289b7c90724ececc122d2a05c7cae3af2cf62
Signed-off-by: Evan Benn <evanbenn@chromium.org>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/67719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Nikolai Artemiev <nartemiev@google.com>
This commit is contained in:
Evan Benn 2022-09-13 16:01:10 +10:00 committed by Edward O'Callaghan
parent 7c9cd29460
commit 2f0e49c2ab
1 changed files with 12 additions and 1 deletions
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13
flashchips.c
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@ -18393,7 +18393,7 @@ const struct flashchip flashchips[] = {
.page_size = 256, .page_size = 256,
/* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */ /* OTP: 256B total; read 0x48; write 0x42, erase 0x44, read ID 0x4B */
/* QPI enable 0x38, disable 0xFF */ /* QPI enable 0x38, disable 0xFF */
.feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI, .feature_bits = FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_QPI | FEATURE_WRSR2 | FEATURE_WRSR3,
.tested = TEST_OK_PREW, .tested = TEST_OK_PREW,
.probe = PROBE_SPI_RDID, .probe = PROBE_SPI_RDID,
.probe_timing = TIMING_ZERO, .probe_timing = TIMING_ZERO,
@ -18421,6 +18421,17 @@ const struct flashchip flashchips[] = {
.write = SPI_CHIP_WRITE256, .write = SPI_CHIP_WRITE256,
.read = SPI_CHIP_READ, .read = SPI_CHIP_READ,
.voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */ .voltage = {1700, 1950}, /* Fast read (0x0B) and multi I/O supported */
.reg_bits =
{
.srp = {STATUS1, 7, RW},
.srl = {STATUS2, 0, RW},
.bp = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}},
.tb = {STATUS1, 5, RW},
.sec = {STATUS1, 6, RW},
.cmp = {STATUS2, 6, RW},
.wps = {STATUS3, 2, RW},
},
.decode_range = DECODE_RANGE_SPI25,
}, },
{ {