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Code Issues Releases Wiki Activity

Convert various prints to use msg_p* and msg_g* respectively

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Convert programmer print messages to msg_p* convert general print messages to msg_g* a few fixes as suggested by Carl-Daniel.

Corresponding to flashrom svn r997.

Signed-off-by: Sean Nelson <audiohacked@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
This commit is contained in:
Sean Nelson 2010-05-07 20:09:04 +00:00
parent 270237687a
commit 316a29f33f
10 changed files with 308 additions and 317 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

93
board_enable.c
View File

@ -87,7 +87,7 @@ static int enable_flash_decode_superio(void)
ret = 0;
break;
default:
printf_debug("Unhandled Super I/O type!\n");
msg_pdbg("Unhandled Super I/O type!\n");
ret = -1;
break;
}
@ -108,7 +108,7 @@ static int w83627hf_gpio24_raise(uint16_t port, const char *name)
/* Is this the W83627HF? */
if (sio_read(port, 0x20) != 0x52) { /* Super I/O device ID reg. */
fprintf(stderr, "\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
msg_perr("\nERROR: %s: W83627HF: Wrong ID: 0x%02X.\n",
name, sio_read(port, 0x20));
w836xx_ext_leave(port);
return -1;
@ -148,7 +148,7 @@ static int w83627thf_gpio4_4_raise(uint16_t port, const char *name)
/* Is this the W83627THF? */
if (sio_read(port, 0x20) != 0x82) { /* Super I/O device ID reg. */
fprintf(stderr, "\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
msg_perr("\nERROR: %s: W83627THF: Wrong ID: 0x%02X.\n",
name, sio_read(port, 0x20));
w836xx_ext_leave(port);
return -1;
@ -253,20 +253,20 @@ static int pc87360_gpio_set(uint8_t gpio, int raise)
uint8_t id, val;
if (gpio_bank > 4) {
fprintf(stderr, "PC87360: Invalid GPIO %d\n", gpio);
msg_perr("PC87360: Invalid GPIO %d\n", gpio);
return -1;
}
id = sio_read(0x2E, 0x20);
if (id != 0xE1) {
fprintf(stderr, "PC87360: unexpected ID %02x\n", id);
msg_perr("PC87360: unexpected ID %02x\n", id);
return -1;
}
sio_write(0x2E, 0x07, 0x07); /* Select GPIO device */
baseport = (sio_read(0x2E, 0x60) << 8) | sio_read(0x2E, 0x61);
if ((baseport & 0xFFF0) == 0xFFF0 || baseport == 0) {
fprintf (stderr, "PC87360: invalid GPIO base address %04x\n",
msg_perr("PC87360: invalid GPIO base address %04x\n",
baseport);
return -1;
}
@ -300,7 +300,7 @@ static int via_vt823x_gpio_set(uint8_t gpio, int raise)
case 0x3337: /* VT8237A */
break;
default:
fprintf(stderr, "\nERROR: VT823x ISA bridge not found.\n");
msg_perr("\nERROR: VT823x ISA bridge not found.\n");
return -1;
}
@ -319,7 +319,7 @@ static int via_vt823x_gpio_set(uint8_t gpio, int raise)
val |= 0x01;
pci_write_byte(dev, 0xE4, val);
} else {
fprintf(stderr, "\nERROR: "
msg_perr("\nERROR: "
"VT823x GPIO%02d is not implemented.\n", gpio);
return -1;
}
@ -411,7 +411,7 @@ static int board_asus_p5a(const char *name)
}
if (i == ASUSP5A_LOOP) {
printf("%s: Unable to contact device.\n", name);
msg_perr("%s: Unable to contact device.\n", name);
return -1;
}
@ -427,7 +427,7 @@ static int board_asus_p5a(const char *name)
}
if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
printf("%s: failed to read device.\n", name);
msg_perr("%s: failed to read device.\n", name);
return -1;
}
@ -454,7 +454,7 @@ static int board_asus_p5a(const char *name)
}
if ((i == ASUSP5A_LOOP) || !(tmp & 0x10)) {
printf("%s: failed to write to device.\n", name);
msg_perr("%s: failed to write to device.\n", name);
return -1;
}
@ -492,8 +492,7 @@ static int board_shuttle_fn25(const char *name)
dev = pci_dev_find(0x10DE, 0x0050); /* NVIDIA CK804 ISA Bridge. */
if (!dev) {
fprintf(stderr,
"\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
msg_perr("\nERROR: NVIDIA nForce4 ISA bridge not found.\n");
return -1;
}
@ -513,7 +512,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise)
uint8_t tmp;
if ((gpio < 0) || (gpio >= 0x40)) {
fprintf(stderr, "\nERROR: unsupported GPIO: %d.\n", gpio);
msg_perr("\nERROR: unsupported GPIO: %d.\n", gpio);
return -1;
}
@ -531,8 +530,7 @@ static int nvidia_mcp_gpio_set(int gpio, int raise)
case 0x0264: /* MCP51 */
break;
default:
fprintf(stderr,
"\nERROR: no NVIDIA LPC/SMBus controller found.\n");
msg_perr("\nERROR: no NVIDIA LPC/SMBus controller found.\n");
return -1;
}
break;
@ -661,20 +659,20 @@ static int intel_piix4_gpo_set(unsigned int gpo, int raise)
dev = pci_dev_find(0x8086, 0x7110); /* Intel PIIX4 ISA bridge */
if (!dev) {
fprintf(stderr, "\nERROR: Intel PIIX4 ISA bridge not found.\n");
msg_perr("\nERROR: Intel PIIX4 ISA bridge not found.\n");
return -1;
}
/* sanity check */
if (gpo > 30) {
fprintf(stderr, "\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
msg_perr("\nERROR: Intel PIIX4 has no GPO%d.\n", gpo);
return -1;
}
/* these are dual function pins which are most likely in use already */
if (((gpo >= 1) && (gpo <= 7)) ||
((gpo >= 9) && (gpo <= 21)) || (gpo == 29)) {
fprintf(stderr, "\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
msg_perr("\nERROR: Unsupported PIIX4 GPO%d.\n", gpo);
return -1;
}
@ -703,7 +701,7 @@ static int intel_piix4_gpo_set(unsigned int gpo, int raise)
dev = pci_dev_find(0x8086, 0x7113); /* Intel PIIX4 PM */
if (!dev) {
fprintf(stderr, "\nERROR: Intel PIIX4 PM not found.\n");
msg_perr("\nERROR: Intel PIIX4 PM not found.\n");
return -1;
}
@ -805,7 +803,7 @@ static int intel_ich_gpio_set(int gpio, int raise)
}
if (!dev) {
fprintf(stderr, "\nERROR: No Known Intel LPC Bridge found.\n");
msg_perr("\nERROR: No Known Intel LPC Bridge found.\n");
return -1;
}
@ -823,12 +821,12 @@ static int intel_ich_gpio_set(int gpio, int raise)
allowed = (intel_ich_gpio_table[i].bank2 >> (gpio - 64)) & 0x01;
if (!allowed) {
fprintf(stderr, "\nERROR: This Intel LPC Bridge does not allow"
msg_perr("\nERROR: This Intel LPC Bridge does not allow"
" setting GPIO%02d\n", gpio);
return -1;
}
printf("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
msg_pdbg("\nIntel ICH LPC Bridge: %sing GPIO%02d.\n",
raise ? "Rais" : "Dropp", gpio);
if (gpio < 32) {
@ -847,7 +845,7 @@ static int intel_ich_gpio_set(int gpio, int raise)
if (dev->device_id > 0x2800) {
tmp = INL(base);
if (!(tmp & (1 << gpio))) {
fprintf(stderr, "\nERROR: This Intel LPC Bridge"
msg_perr("\nERROR: This Intel LPC Bridge"
" does not allow setting GPIO%02d\n",
gpio);
return -1;
@ -879,7 +877,7 @@ static int intel_ich_gpio_set(int gpio, int raise)
if (dev->device_id > 0x2800) {
tmp = INL(base + 30);
if (!(tmp & (1 << gpio))) {
fprintf(stderr, "\nERROR: This Intel LPC Bridge"
msg_perr("\nERROR: This Intel LPC Bridge"
" does not allow setting GPIO%02d\n",
gpio + 32);
return -1;
@ -908,7 +906,7 @@ static int intel_ich_gpio_set(int gpio, int raise)
tmp = INL(base + 40);
if (!(tmp & (1 << gpio))) {
fprintf(stderr, "\nERROR: This Intel LPC Bridge does "
msg_perr("\nERROR: This Intel LPC Bridge does "
"not allow setting GPIO%02d\n", gpio + 64);
return -1;
}
@ -1051,11 +1049,11 @@ static int via_apollo_gpo_set(int gpio, int raise)
/* VT82C686 Power management */
dev = pci_dev_find(0x1106, 0x3057);
if (!dev) {
fprintf(stderr, "\nERROR: VT82C686 PM device not found.\n");
msg_perr("\nERROR: VT82C686 PM device not found.\n");
return -1;
}
printf("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
msg_pdbg("\nVIA Apollo ACPI: %sing GPIO%02d.\n",
raise ? "Rais" : "Dropp", gpio);
/* select GPO function on multiplexed pins */
@ -1118,7 +1116,7 @@ static int board_msi_651ml(const char *name)
dev = pci_dev_find(0x1039, 0x0962);
if (!dev) {
fprintf(stderr, "Expected south bridge not found\n");
msg_perr("Expected south bridge not found\n");
return 1;
}
@ -1151,7 +1149,7 @@ static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
/* Verify the chip ID. */
OUTB(0x55, sio_port); /* Enable configuration. */
if (sio_read(sio_port, 0x20) != chip_id) {
fprintf(stderr, "\nERROR: SMSC Super I/O not found.\n");
msg_perr("\nERROR: SMSC Super I/O not found.\n");
goto out;
}
@ -1163,7 +1161,7 @@ static uint16_t smsc_find_runtime(uint16_t sio_port, uint16_t chip_id,
}
if (rt_port == 0) {
fprintf(stderr, "\nERROR: "
msg_perr("\nERROR: "
"Super I/O runtime interface not available.\n");
}
out:
@ -1183,7 +1181,7 @@ static int board_mitac_6513wu(const char *name)
dev = pci_dev_find(0x8086, 0x2410); /* Intel 82801AA ISA bridge */
if (!dev) {
fprintf(stderr, "\nERROR: Intel 82801AA ISA bridge not found.\n");
msg_perr("\nERROR: Intel 82801AA ISA bridge not found.\n");
return -1;
}
@ -1218,7 +1216,7 @@ static int board_asus_a7v8x(const char *name)
w836xx_ext_leave(0x2E);
if (id != 0x8701) {
fprintf(stderr, "\nERROR: IT8703F Super I/O not found.\n");
msg_perr("\nERROR: IT8703F Super I/O not found.\n");
return -1;
}
@ -1229,7 +1227,7 @@ static int board_asus_a7v8x(const char *name)
w836xx_ext_leave(0x2E);
if (!base) {
fprintf(stderr, "\nERROR: Failed to read IT8703F Super I/O GPIO"
msg_perr("\nERROR: Failed to read IT8703F Super I/O GPIO"
" Base.\n");
return -1;
}
@ -1259,8 +1257,7 @@ static int it8712f_gpio_set(unsigned int line, int raise)
/* Check line */
if ((port > 4) || /* also catches unsigned -1 */
((port < 4) && (line > 7)) || ((port == 4) && (line > 5))) {
fprintf(stderr,
"\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line);
msg_perr("\nERROR: Unsupported IT8712F GPIO Line %02d.\n", line);
return -1;
}
@ -1270,7 +1267,7 @@ static int it8712f_gpio_set(unsigned int line, int raise)
exit_conf_mode_ite(0x2E);
if (id != 0x8712) {
fprintf(stderr, "\nERROR: IT8712F Super I/O not found.\n");
msg_perr("\nERROR: IT8712F Super I/O not found.\n");
return -1;
}
@ -1281,7 +1278,7 @@ static int it8712f_gpio_set(unsigned int line, int raise)
exit_conf_mode_ite(0x2E);
if (!base) {
fprintf(stderr, "\nERROR: Failed to read IT8712F Super I/O GPIO"
msg_perr("\nERROR: Failed to read IT8712F Super I/O GPIO"
" Base.\n");
return -1;
}
@ -1450,10 +1447,10 @@ static struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
if (partmatch) {
/* a second entry has a matching part name */
printf("AMBIGUOUS BOARD NAME: %s\n", part);
printf("At least vendors '%s' and '%s' match.\n",
msg_pinfo("AMBIGUOUS BOARD NAME: %s\n", part);
msg_pinfo("At least vendors '%s' and '%s' match.\n",
partmatch->lb_vendor, board->lb_vendor);
printf("Please use the full -m vendor:part syntax.\n");
msg_perr("Please use the full -m vendor:part syntax.\n");
return NULL;
}
partmatch = board;
@ -1467,7 +1464,7 @@ static struct board_pciid_enable *board_match_coreboot_name(const char *vendor,
* coreboot table. If it was, the coreboot implementor is
* expected to fix flashrom, too.
*/
printf("\nUnknown vendor:board from -m option: %s:%s\n\n",
msg_perr("\nUnknown vendor:board from -m option: %s:%s\n\n",
vendor, part);
}
return NULL;
@ -1507,7 +1504,7 @@ static struct board_pciid_enable *board_match_pci_card_ids(void)
if (board->dmi_pattern) {
if (!has_dmi_support) {
fprintf(stderr, "WARNING: Can't autodetect %s %s,"
msg_perr("WARNING: Can't autodetect %s %s,"
" DMI info unavailable.\n",
board->vendor_name, board->board_name);
continue;
@ -1536,7 +1533,7 @@ int board_flash_enable(const char *vendor, const char *part)
if (board && board->status == NT) {
if (!force_boardenable) {
printf("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
msg_pinfo("WARNING: Your mainboard is %s %s, but the mainboard-specific\n"
"code has not been tested, and thus will not not be executed by default.\n"
"Depending on your hardware environment, erasing, writing or even probing\n"
"can fail without running the board specific code.\n\n"
@ -1545,7 +1542,7 @@ int board_flash_enable(const char *vendor, const char *part)
board->vendor_name, board->board_name);
board = NULL;
} else {
printf("NOTE: Running an untested board enable procedure.\n"
msg_pinfo("NOTE: Running an untested board enable procedure.\n"
"Please report success/failure to flashrom@flashrom.org.\n");
}
}
@ -1556,15 +1553,15 @@ int board_flash_enable(const char *vendor, const char *part)
board->max_rom_decode_parallel * 1024;
if (board->enable != NULL) {
printf("Disabling flash write protection for "
msg_pinfo("Disabling flash write protection for "
"board \"%s %s\"... ", board->vendor_name,
board->board_name);
ret = board->enable(board->vendor_name);
if (ret)
printf("FAILED!\n");
msg_pinfo("FAILED!\n");
else
printf("OK.\n");
msg_pinfo("OK.\n");
}
}

22
cbtable.c
View File

@ -112,29 +112,29 @@ static struct lb_header *find_lb_table(void *base, unsigned long start,
(struct lb_record *)(((char *)base) + addr + sizeof(*head));
if (memcmp(head->signature, "LBIO", 4) != 0)
continue;
printf_debug("Found candidate at: %08lx-%08lx\n",
msg_pdbg("Found candidate at: %08lx-%08lx\n",
addr, addr + head->table_bytes);
if (head->header_bytes != sizeof(*head)) {
fprintf(stderr, "Header bytes of %d are incorrect.\n",
msg_perr("Header bytes of %d are incorrect.\n",
head->header_bytes);
continue;
}
if (count_lb_records(head) != head->table_entries) {
fprintf(stderr, "Bad record count: %d.\n",
msg_perr("Bad record count: %d.\n",
head->table_entries);
continue;
}
if (compute_checksum((uint8_t *) head, sizeof(*head)) != 0) {
fprintf(stderr, "Bad header checksum.\n");
msg_perr("Bad header checksum.\n");
continue;
}
if (compute_checksum(recs, head->table_bytes)
!= head->table_checksum) {
fprintf(stderr, "Bad table checksum: %04x.\n",
msg_perr("Bad table checksum: %04x.\n",
head->table_checksum);
continue;
}
printf_debug("Found coreboot table at 0x%08lx.\n", addr);
msg_pdbg("Found coreboot table at 0x%08lx.\n", addr);
return head;
};
@ -150,7 +150,7 @@ static void find_mainboard(struct lb_record *ptr, unsigned long addr)
rec = (struct lb_mainboard *)ptr;
max_size = rec->size - sizeof(*rec);
printf("Vendor ID: %.*s, part ID: %.*s\n",
msg_pdbg("Vendor ID: %.*s, part ID: %.*s\n",
max_size - rec->vendor_idx,
rec->strings + rec->vendor_idx,
max_size - rec->part_number_idx,
@ -161,7 +161,7 @@ static void find_mainboard(struct lb_record *ptr, unsigned long addr)
rec->strings + rec->part_number_idx);
if (lb_part) {
printf("Overwritten by command line, vendor ID: %s, part ID: %s.\n", lb_vendor, lb_part);
msg_pdbg("Overwritten by command line, vendor ID: %s, part ID: %s.\n", lb_vendor, lb_part);
} else {
partvendor_from_cbtable = 1;
lb_part = strdup(part);
@ -235,16 +235,16 @@ int coreboot_init(void)
}
if (!lb_table) {
printf("No coreboot table found.\n");
msg_pinfo("No coreboot table found.\n");
return -1;
}
addr = ((char *)lb_table) - ((char *)table_area) + start;
fprintf(stdout, "coreboot table found at 0x%lx.\n",
msg_pinfo("coreboot table found at 0x%lx.\n",
(unsigned long)lb_table - (unsigned long)table_area + start);
rec = (struct lb_record *)(((char *)lb_table) + lb_table->header_bytes);
last = (struct lb_record *)(((char *)rec) + lb_table->table_bytes);
printf_debug("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n",
msg_pdbg("coreboot header(%d) checksum: %04x table(%d) checksum: %04x entries: %d\n",
lb_table->header_bytes, lb_table->header_checksum,
lb_table->table_bytes, lb_table->table_checksum,
lb_table->table_entries);

216
chipset_enable.c
View File

@ -74,8 +74,8 @@ static int enable_flash_sis_mapping(struct pci_dev *dev, const char *name)
pci_write_byte(dev, 0x40, new);
newer = pci_read_byte(dev, 0x40);
if (newer != new) {
printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
printf_debug("Stuck at 0x%x\n", newer);
msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
msg_pinfo("Stuck at 0x%x\n", newer);
return -1;
}
return 0;
@ -91,9 +91,9 @@ static struct pci_dev *find_southbridge(uint16_t vendor, const char *name)
if (!sbdev)
sbdev = pci_dev_find_vendorclass(vendor, 0x0000);
if (!sbdev)
fprintf(stderr, "No southbridge found for %s!\n", name);
msg_perr("No southbridge found for %s!\n", name);
if (sbdev)
printf_debug("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
msg_pdbg("Found southbridge %04x:%04x at %02x:%02x:%01x\n",
sbdev->vendor_id, sbdev->device_id,
sbdev->bus, sbdev->dev, sbdev->func);
return sbdev;
@ -162,8 +162,8 @@ static int enable_flash_sis530(struct pci_dev *dev, const char *name)
pci_write_byte(sbdev, 0x45, new);
newer = pci_read_byte(sbdev, 0x45);
if (newer != new) {
printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
printf_debug("Stuck at 0x%x\n", newer);
msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
msg_pinfo("Stuck at 0x%x\n", newer);
ret = -1;
}
@ -188,8 +188,8 @@ static int enable_flash_sis540(struct pci_dev *dev, const char *name)
pci_write_byte(sbdev, 0x45, new);
newer = pci_read_byte(sbdev, 0x45);
if (newer != new) {
printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
printf_debug("Stuck at 0x%x\n", newer);
msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x45, new, name);
msg_pinfo("Stuck at 0x%x\n", newer);
ret = -1;
}
@ -235,7 +235,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
pci_write_word(dev, xbcs, new);
if (pci_read_word(dev, xbcs) != new) {
printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", xbcs, new, name);
return -1;
}
@ -257,11 +257,11 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name,
*/
old = pci_read_byte(dev, bios_cntl);
printf_debug("\nBIOS Lock Enable: %sabled, ",
msg_pdbg("\nBIOS Lock Enable: %sabled, ",
(old & (1 << 1)) ? "en" : "dis");
printf_debug("BIOS Write Enable: %sabled, ",
msg_pdbg("BIOS Write Enable: %sabled, ",
(old & (1 << 0)) ? "en" : "dis");
printf_debug("BIOS_CNTL is 0x%x\n", old);
msg_pdbg("BIOS_CNTL is 0x%x\n", old);
new = old | 1;
@ -271,7 +271,7 @@ static int enable_flash_ich(struct pci_dev *dev, const char *name,
pci_write_byte(dev, bios_cntl, new);
if (pci_read_byte(dev, bios_cntl) != new) {
printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", bios_cntl, new, name);
return -1;
}
@ -306,7 +306,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
fwh_conf = (uint32_t)strtoul(idsel, NULL, 0);
/* FIXME: Need to undo this on shutdown. */
printf("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf);
msg_pinfo("\nSetting IDSEL=0x%x for top 16 MB", fwh_conf);
pci_write_long(dev, 0xd0, fwh_conf);
pci_write_word(dev, 0xd4, fwh_conf);
/* FIXME: Decode settings are not changed. */
@ -321,7 +321,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
fwh_conf = pci_read_long(dev, 0xd0);
for (i = 7; i >= 0; i--) {
tmp = (fwh_conf >> (i * 4)) & 0xf;
printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
(0x1ff8 + i) * 0x80000,
(0x1ff0 + i) * 0x80000,
tmp);
@ -335,7 +335,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
fwh_conf = pci_read_word(dev, 0xd4);
for (i = 3; i >= 0; i--) {
tmp = (fwh_conf >> (i * 4)) & 0xf;
printf_debug("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
msg_pdbg("\n0x%08x/0x%08x FWH IDSEL: 0x%x",
(0xff4 + i) * 0x100000,
(0xff0 + i) * 0x100000,
tmp);
@ -350,7 +350,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
fwh_conf = pci_read_word(dev, 0xd8);
for (i = 7; i >= 0; i--) {
tmp = (fwh_conf >> (i + 0x8)) & 0x1;
printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
(0x1ff8 + i) * 0x80000,
(0x1ff0 + i) * 0x80000,
tmp ? "en" : "dis");
@ -362,7 +362,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
}
for (i = 3; i >= 0; i--) {
tmp = (fwh_conf >> i) & 0x1;
printf_debug("\n0x%08x/0x%08x FWH decode %sabled",
msg_pdbg("\n0x%08x/0x%08x FWH decode %sabled",
(0xff4 + i) * 0x100000,
(0xff0 + i) * 0x100000,
tmp ? "en" : "dis");
@ -373,7 +373,7 @@ static int enable_flash_ich_dc(struct pci_dev *dev, const char *name)
}
}
max_rom_decode.fwh = min(max_decode_fwh_idsel, max_decode_fwh_decode);
printf_debug("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
msg_pdbg("\nMaximum FWH chip size: 0x%x bytes", max_rom_decode.fwh);
/* If we're called by enable_flash_ich_dc_spi, it will override
* buses_supported anyway.
@ -391,7 +391,7 @@ static int enable_flash_poulsbo(struct pci_dev *dev, const char *name)
return err;
old = pci_read_byte(dev, 0xd9);
printf_debug("BIOS Prefetch Enable: %sabled, ",
msg_pdbg("BIOS Prefetch Enable: %sabled, ",
(old & 1) ? "en" : "dis");
new = old & ~1;
@ -413,10 +413,10 @@ static int enable_flash_vt8237s_spi(struct pci_dev *dev, const char *name)
/* Do we really need no write enable? */
mmio_base = (pci_read_long(dev, 0xbc)) << 8;
printf_debug("MMIO base at = 0x%x\n", mmio_base);
msg_pdbg("MMIO base at = 0x%x\n", mmio_base);
spibar = physmap("VT8237S MMIO registers", mmio_base, 0x70);
printf_debug("0x6c: 0x%04x (CLOCK/DEBUG)\n",
msg_pdbg("0x6c: 0x%04x (CLOCK/DEBUG)\n",
mmio_readw(spibar + 0x6c));
/* Not sure if it speaks all these bus protocols. */
@ -444,20 +444,20 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
/* Get physical address of Root Complex Register Block */
tmp = pci_read_long(dev, 0xf0) & 0xffffc000;
printf_debug("\nRoot Complex Register Block address = 0x%x\n", tmp);
msg_pdbg("\nRoot Complex Register Block address = 0x%x\n", tmp);
/* Map RCBA to virtual memory */
rcrb = physmap("ICH RCRB", tmp, 0x4000);
gcs = mmio_readl(rcrb + 0x3410);
printf_debug("GCS = 0x%x: ", gcs);
printf_debug("BIOS Interface Lock-Down: %sabled, ",
msg_pdbg("GCS = 0x%x: ", gcs);
msg_pdbg("BIOS Interface Lock-Down: %sabled, ",
(gcs & 0x1) ? "en" : "dis");
bbs = (gcs >> 10) & 0x3;
printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
msg_pdbg("BOOT BIOS Straps: 0x%x (%s)\n", bbs, straps_names[bbs]);
buc = mmio_readb(rcrb + 0x3414);
printf_debug("Top Swap : %s\n",
msg_pdbg("Top Swap : %s\n",
(buc & 1) ? "enabled (A16 inverted)" : "not enabled");
/* It seems the ICH7 does not support SPI and LPC chips at the same
@ -492,105 +492,105 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
}
/* SPIBAR is at RCRB+0x3020 for ICH[78] and RCRB+0x3800 for ICH9. */
printf_debug("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
msg_pdbg("SPIBAR = 0x%x + 0x%04x\n", tmp, spibar_offset);
/* Assign Virtual Address */
spibar = rcrb + spibar_offset;
switch (spi_controller) {
case SPI_CONTROLLER_ICH7:
printf_debug("0x00: 0x%04x (SPIS)\n",
msg_pdbg("0x00: 0x%04x (SPIS)\n",
mmio_readw(spibar + 0));
printf_debug("0x02: 0x%04x (SPIC)\n",
msg_pdbg("0x02: 0x%04x (SPIC)\n",
mmio_readw(spibar + 2));
printf_debug("0x04: 0x%08x (SPIA)\n",
msg_pdbg("0x04: 0x%08x (SPIA)\n",
mmio_readl(spibar + 4));
for (i = 0; i < 8; i++) {
int offs;
offs = 8 + (i * 8);
printf_debug("0x%02x: 0x%08x (SPID%d)\n", offs,
msg_pdbg("0x%02x: 0x%08x (SPID%d)\n", offs,
mmio_readl(spibar + offs), i);
printf_debug("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
msg_pdbg("0x%02x: 0x%08x (SPID%d+4)\n", offs + 4,
mmio_readl(spibar + offs + 4), i);
}
printf_debug("0x50: 0x%08x (BBAR)\n",
msg_pdbg("0x50: 0x%08x (BBAR)\n",
mmio_readl(spibar + 0x50));
printf_debug("0x54: 0x%04x (PREOP)\n",
msg_pdbg("0x54: 0x%04x (PREOP)\n",
mmio_readw(spibar + 0x54));
printf_debug("0x56: 0x%04x (OPTYPE)\n",
msg_pdbg("0x56: 0x%04x (OPTYPE)\n",
mmio_readw(spibar + 0x56));
printf_debug("0x58: 0x%08x (OPMENU)\n",
msg_pdbg("0x58: 0x%08x (OPMENU)\n",
mmio_readl(spibar + 0x58));
printf_debug("0x5c: 0x%08x (OPMENU+4)\n",
msg_pdbg("0x5c: 0x%08x (OPMENU+4)\n",
mmio_readl(spibar + 0x5c));
for (i = 0; i < 4; i++) {
int offs;
offs = 0x60 + (i * 4);
printf_debug("0x%02x: 0x%08x (PBR%d)\n", offs,
msg_pdbg("0x%02x: 0x%08x (PBR%d)\n", offs,
mmio_readl(spibar + offs), i);
}
printf_debug("\n");
msg_pdbg("\n");
if (mmio_readw(spibar) & (1 << 15)) {
printf("WARNING: SPI Configuration Lockdown activated.\n");
msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
ichspi_lock = 1;
}
ich_init_opcodes();
break;
case SPI_CONTROLLER_ICH9:
tmp2 = mmio_readw(spibar + 4);
printf_debug("0x04: 0x%04x (HSFS)\n", tmp2);
printf_debug("FLOCKDN %i, ", (tmp2 >> 15 & 1));
printf_debug("FDV %i, ", (tmp2 >> 14) & 1);
printf_debug("FDOPSS %i, ", (tmp2 >> 13) & 1);
printf_debug("SCIP %i, ", (tmp2 >> 5) & 1);
printf_debug("BERASE %i, ", (tmp2 >> 3) & 3);
printf_debug("AEL %i, ", (tmp2 >> 2) & 1);
printf_debug("FCERR %i, ", (tmp2 >> 1) & 1);
printf_debug("FDONE %i\n", (tmp2 >> 0) & 1);
msg_pdbg("0x04: 0x%04x (HSFS)\n", tmp2);
msg_pdbg("FLOCKDN %i, ", (tmp2 >> 15 & 1));
msg_pdbg("FDV %i, ", (tmp2 >> 14) & 1);
msg_pdbg("FDOPSS %i, ", (tmp2 >> 13) & 1);
msg_pdbg("SCIP %i, ", (tmp2 >> 5) & 1);
msg_pdbg("BERASE %i, ", (tmp2 >> 3) & 3);
msg_pdbg("AEL %i, ", (tmp2 >> 2) & 1);
msg_pdbg("FCERR %i, ", (tmp2 >> 1) & 1);
msg_pdbg("FDONE %i\n", (tmp2 >> 0) & 1);
tmp = mmio_readl(spibar + 0x50);
printf_debug("0x50: 0x%08x (FRAP)\n", tmp);
printf_debug("BMWAG %i, ", (tmp >> 24) & 0xff);
printf_debug("BMRAG %i, ", (tmp >> 16) & 0xff);
printf_debug("BRWA %i, ", (tmp >> 8) & 0xff);
printf_debug("BRRA %i\n", (tmp >> 0) & 0xff);
msg_pdbg("0x50: 0x%08x (FRAP)\n", tmp);
msg_pdbg("BMWAG %i, ", (tmp >> 24) & 0xff);
msg_pdbg("BMRAG %i, ", (tmp >> 16) & 0xff);
msg_pdbg("BRWA %i, ", (tmp >> 8) & 0xff);
msg_pdbg("BRRA %i\n", (tmp >> 0) & 0xff);
printf_debug("0x54: 0x%08x (FREG0)\n",
msg_pdbg("0x54: 0x%08x (FREG0)\n",
mmio_readl(spibar + 0x54));
printf_debug("0x58: 0x%08x (FREG1)\n",
msg_pdbg("0x58: 0x%08x (FREG1)\n",
mmio_readl(spibar + 0x58));
printf_debug("0x5C: 0x%08x (FREG2)\n",
msg_pdbg("0x5C: 0x%08x (FREG2)\n",
mmio_readl(spibar + 0x5C));
printf_debug("0x60: 0x%08x (FREG3)\n",
msg_pdbg("0x60: 0x%08x (FREG3)\n",
mmio_readl(spibar + 0x60));
printf_debug("0x64: 0x%08x (FREG4)\n",
msg_pdbg("0x64: 0x%08x (FREG4)\n",
mmio_readl(spibar + 0x64));
printf_debug("0x74: 0x%08x (PR0)\n",
msg_pdbg("0x74: 0x%08x (PR0)\n",
mmio_readl(spibar + 0x74));
printf_debug("0x78: 0x%08x (PR1)\n",
msg_pdbg("0x78: 0x%08x (PR1)\n",
mmio_readl(spibar + 0x78));
printf_debug("0x7C: 0x%08x (PR2)\n",
msg_pdbg("0x7C: 0x%08x (PR2)\n",
mmio_readl(spibar + 0x7C));
printf_debug("0x80: 0x%08x (PR3)\n",
msg_pdbg("0x80: 0x%08x (PR3)\n",
mmio_readl(spibar + 0x80));
printf_debug("0x84: 0x%08x (PR4)\n",
msg_pdbg("0x84: 0x%08x (PR4)\n",
mmio_readl(spibar + 0x84));
printf_debug("0x90: 0x%08x (SSFS, SSFC)\n",
msg_pdbg("0x90: 0x%08x (SSFS, SSFC)\n",
mmio_readl(spibar + 0x90));
printf_debug("0x94: 0x%04x (PREOP)\n",
msg_pdbg("0x94: 0x%04x (PREOP)\n",
mmio_readw(spibar + 0x94));
printf_debug("0x96: 0x%04x (OPTYPE)\n",
msg_pdbg("0x96: 0x%04x (OPTYPE)\n",
mmio_readw(spibar + 0x96));
printf_debug("0x98: 0x%08x (OPMENU)\n",
msg_pdbg("0x98: 0x%08x (OPMENU)\n",
mmio_readl(spibar + 0x98));
printf_debug("0x9C: 0x%08x (OPMENU+4)\n",
msg_pdbg("0x9C: 0x%08x (OPMENU+4)\n",
mmio_readl(spibar + 0x9C));
printf_debug("0xA0: 0x%08x (BBAR)\n",
msg_pdbg("0xA0: 0x%08x (BBAR)\n",
mmio_readl(spibar + 0xA0));
printf_debug("0xB0: 0x%08x (FDOC)\n",
msg_pdbg("0xB0: 0x%08x (FDOC)\n",
mmio_readl(spibar + 0xB0));
if (tmp2 & (1 << 15)) {
printf("WARNING: SPI Configuration Lockdown activated.\n");
msg_pinfo("WARNING: SPI Configuration Lockdown activated.\n");
ichspi_lock = 1;
}
ich_init_opcodes();
@ -601,18 +601,18 @@ static int enable_flash_ich_dc_spi(struct pci_dev *dev, const char *name,
}
old = pci_read_byte(dev, 0xdc);
printf_debug("SPI Read Configuration: ");
msg_pdbg("SPI Read Configuration: ");
new = (old >> 2) & 0x3;
switch (new) {
case 0:
case 1:
case 2:
printf_debug("prefetching %sabled, caching %sabled, ",
msg_pdbg("prefetching %sabled, caching %sabled, ",
(new & 0x2) ? "en" : "dis",
(new & 0x1) ? "dis" : "en");
break;
default:
printf_debug("invalid prefetching/caching settings, ");
msg_pdbg("invalid prefetching/caching settings, ");
break;
}
@ -652,7 +652,7 @@ static int enable_flash_vt823x(struct pci_dev *dev, const char *name)
pci_write_byte(dev, 0x40, val);
if (pci_read_byte(dev, 0x40) != val) {
printf("\nWARNING: Failed to enable flash write on \"%s\"\n",
msg_pinfo("\nWARNING: Failed to enable flash write on \"%s\"\n",
name);
return -1;
}
@ -769,7 +769,7 @@ static int enable_flash_sc1100(struct pci_dev *dev, const char *name)
new = pci_read_byte(dev, 0x52);
if (new != 0xee) {
printf_debug("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
msg_pinfo("tried to set register 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x52, new, name);
return -1;
}
@ -787,7 +787,7 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
if (new != old) {
pci_write_byte(dev, 0x43, new);
if (pci_read_byte(dev, 0x43) != new) {
printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x43, new, name);
}
}
@ -799,7 +799,7 @@ static int enable_flash_amd8111(struct pci_dev *dev, const char *name)
pci_write_byte(dev, 0x40, new);
if (pci_read_byte(dev, 0x40) != new) {
printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x40, new, name);
return -1;
}
@ -819,7 +819,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
/* No protection flags for this region?*/
if ((prot & 0x3) == 0)
continue;
printf_debug("SB600 %s%sprotected from %u to %u\n",
msg_pinfo("SB600 %s%sprotected from %u to %u\n",
(prot & 0x1) ? "write " : "",
(prot & 0x2) ? "read " : "",
(prot & 0xfffffc00),
@ -828,7 +828,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
pci_write_byte(dev, reg, prot);
prot = pci_read_long(dev, reg);
if (prot & 0x3)
printf("SB600 %s%sunprotect failed from %u to %u\n",
msg_perr("SB600 %s%sunprotect failed from %u to %u\n",
(prot & 0x1) ? "write " : "",
(prot & 0x2) ? "read " : "",
(prot & 0xfffffc00),
@ -838,7 +838,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
/* Read SPI_BaseAddr */
tmp = pci_read_long(dev, 0xa0);
tmp &= 0xffffffe0; /* remove bits 4-0 (reserved) */
printf_debug("SPI base address is at 0x%x\n", tmp);
msg_pdbg("SPI base address is at 0x%x\n", tmp);
/* If the BAR has address 0, it is unlikely SPI is used. */
if (!tmp)
@ -854,17 +854,17 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
sb600_spibar += tmp & 0xfff;
tmp = pci_read_long(dev, 0xa0);
printf_debug("AltSpiCSEnable=%i, SpiRomEnable=%i, "
msg_pdbg("AltSpiCSEnable=%i, SpiRomEnable=%i, "
"AbortEnable=%i\n", tmp & 0x1, (tmp & 0x2) >> 1,
(tmp & 0x4) >> 2);
tmp = (pci_read_byte(dev, 0xba) & 0x4) >> 2;
printf_debug("PrefetchEnSPIFromIMC=%i, ", tmp);
msg_pdbg("PrefetchEnSPIFromIMC=%i, ", tmp);
tmp = pci_read_byte(dev, 0xbb);
printf_debug("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n",
msg_pdbg("PrefetchEnSPIFromHost=%i, SpiOpEnInLpcMode=%i\n",
tmp & 0x1, (tmp & 0x20) >> 5);
tmp = mmio_readl(sb600_spibar);
printf_debug("SpiArbEnable=%i, SpiAccessMacRomEn=%i, "
msg_pdbg("SpiArbEnable=%i, SpiAccessMacRomEn=%i, "
"SpiHostAccessRomEn=%i, ArbWaitCount=%i, "
"SpiBridgeDisable=%i, DropOneClkOnRd=%i\n",
(tmp >> 19) & 0x1, (tmp >> 22) & 0x1,
@ -876,7 +876,7 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
smbus_dev = pci_dev_find(0x1002, 0x4385);
if (has_spi && !smbus_dev) {
fprintf(stderr, "ERROR: SMBus device not found. Not enabling SPI.\n");
msg_perr("ERROR: SMBus device not found. Not enabling SPI.\n");
has_spi = 0;
}
if (has_spi) {
@ -884,22 +884,22 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
/* GPIO11/SPI_DO and GPIO12/SPI_DI status */
reg = pci_read_byte(smbus_dev, 0xAB);
reg &= 0xC0;
printf_debug("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
printf_debug("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
msg_pdbg("GPIO11 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_DO");
msg_pdbg("GPIO12 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_DI");
if (reg != 0x00)
has_spi = 0;
/* GPIO31/SPI_HOLD and GPIO32/SPI_CS status */
reg = pci_read_byte(smbus_dev, 0x83);
reg &= 0xC0;
printf_debug("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
printf_debug("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
msg_pdbg("GPIO31 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_HOLD");
msg_pdbg("GPIO32 used for %s\n", (reg & (1 << 7)) ? "GPIO" : "SPI_CS");
/* SPI_HOLD is not used on all boards, filter it out. */
if ((reg & 0x80) != 0x00)
has_spi = 0;
/* GPIO47/SPI_CLK status */
reg = pci_read_byte(smbus_dev, 0xA7);
reg &= 0x40;
printf_debug("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
msg_pdbg("GPIO47 used for %s\n", (reg & (1 << 6)) ? "GPIO" : "SPI_CLK");
if (reg != 0x00)
has_spi = 0;
}
@ -914,24 +914,24 @@ static int enable_flash_sb600(struct pci_dev *dev, const char *name)
OUTB(0x8f, 0xcd6);
reg = INB(0xcd7);
reg &= 0x0e;
printf_debug("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
msg_pdbg("ROM strap override is %sactive", (reg & 0x02) ? "" : "not ");
if (reg & 0x02) {
switch ((reg & 0x0c) >> 2) {
case 0x00:
printf_debug(": LPC");
msg_pdbg(": LPC");
break;
case 0x01:
printf_debug(": PCI");
msg_pdbg(": PCI");
break;
case 0x02:
printf_debug(": FWH");
msg_pdbg(": FWH");
break;
case 0x03:
printf_debug(": SPI");
msg_pdbg(": SPI");
break;
}
}
printf_debug("\n");
msg_pdbg("\n");
/* Force enable SPI ROM in SB600 PM register.
* If we enable SPI ROM here, we have to disable it after we leave.
@ -970,7 +970,7 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name)
if (new != old) {
pci_write_byte(dev, 0x88, new);
if (pci_read_byte(dev, 0x88) != new) {
printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x88, new, name);
}
}
@ -981,7 +981,7 @@ static int enable_flash_ck804(struct pci_dev *dev, const char *name)
pci_write_byte(dev, 0x6d, new);
if (pci_read_byte(dev, 0x6d) != new) {
printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
return -1;
}
@ -998,7 +998,7 @@ static int enable_flash_sb400(struct pci_dev *dev, const char *name)
smbusdev = pci_dev_find(0x1002, 0x4372);
if (!smbusdev) {
fprintf(stderr, "ERROR: SMBus device not found. Aborting.\n");
msg_perr("ERROR: SMBus device not found. Aborting.\n");
exit(1);
}
@ -1047,7 +1047,7 @@ static int enable_flash_mcp55(struct pci_dev *dev, const char *name)
pci_write_byte(dev, 0x6d, new);
if (pci_read_byte(dev, 0x6d) != new) {
printf_debug("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
msg_pinfo("tried to set 0x%x to 0x%x on %s failed (WARNING ONLY)\n", 0x6d, new, name);
return -1;
}
@ -1277,7 +1277,7 @@ static int get_flashbase_sc520(struct pci_dev *dev, const char *name)
flashbase = parx << 12;
}
} else {
printf("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
msg_pinfo("AMD Elan SC520 detected, but no BOOTCS. Assuming flash at 4G\n");
}
/* 4. Clean up */
@ -1436,18 +1436,18 @@ int chipset_flash_enable(void)
}
if (dev) {
printf("Found chipset \"%s %s\", enabling flash write... ",
msg_pinfo("Found chipset \"%s %s\", enabling flash write... ",
chipset_enables[i].vendor_name,
chipset_enables[i].device_name);
ret = chipset_enables[i].doit(dev,
chipset_enables[i].device_name);
if (ret)
printf("FAILED!\n");
msg_pinfo("FAILED!\n");
else
printf("OK.\n");
msg_pinfo("OK.\n");
}
printf("This chipset supports the following protocols: %s.\n",
msg_pinfo("This chipset supports the following protocols: %s.\n",
flashbuses_to_text(buses_supported));
return ret;

13
dmi.c
View File

@ -53,12 +53,12 @@ static char *get_dmi_string(const char *string_name)
"%s -s %s", dmidecode_command, string_name);
dmidecode_pipe = popen(commandline, "r");
if (!dmidecode_pipe) {
printf_debug("DMI pipe open error\n");
msg_perr("DMI pipe open error\n");
return NULL;
}
if (!fgets(answerbuf, DMI_MAX_ANSWER_LEN, dmidecode_pipe)) {
if(ferror(dmidecode_pipe)) {
printf_debug("DMI pipe read error\n");
msg_perr("DMI pipe read error\n");
pclose(dmidecode_pipe);
return NULL;
} else {
@ -70,7 +70,8 @@ static char *get_dmi_string(const char *string_name)
while (!feof(dmidecode_pipe))
getc(dmidecode_pipe);
if (pclose(dmidecode_pipe) != 0) {
printf_debug("DMI pipe close error\n");
msg_pinfo("dmidecode execution unsucessfull - continuing "
"without DMI info\n");
return NULL;
}
@ -78,7 +79,7 @@ static char *get_dmi_string(const char *string_name)
if (answerbuf[0] != 0 &&
answerbuf[strlen(answerbuf) - 1] == '\n')
answerbuf[strlen(answerbuf) - 1] = 0;
printf_debug("DMI string %s: \"%s\"\n", string_name, answerbuf);
msg_pdbg("DMI string %s: \"%s\"\n", string_name, answerbuf);
result = strdup(answerbuf);
if (!result)
@ -104,7 +105,7 @@ void dmi_init(void)
chassis_type = get_dmi_string("chassis-type");
if (chassis_type && (!strcmp(chassis_type, "Notebook") ||
!strcmp(chassis_type, "Portable"))) {
printf_debug("Laptop detected via DMI\n");
msg_pdbg("Laptop detected via DMI\n");
is_laptop = 1;
}
free(chassis_type);
@ -126,7 +127,7 @@ static int dmi_compare(const char *value, const char *pattern)
int anchored = 0;
int patternlen;
printf_debug("matching %s against %s\n", value, pattern);
msg_pspew("matching %s against %s\n", value, pattern);
/* The empty string is part of all strings! */
if (pattern[0] == 0)
return 1;

142
flashrom.c
View File

@ -520,7 +520,7 @@ char *extract_param(char **haystack, char *needle, char *delim)
if (devlen) {
dev = malloc(devlen + 1);
if (!dev) {
fprintf(stderr, "Out of memory!\n");
msg_gerr("Out of memory!\n");
exit(1);
}
strncpy(dev, param_pos, devlen);
@ -532,7 +532,7 @@ char *extract_param(char **haystack, char *needle, char *delim)
memmove(param_pos, rest, strlen(rest) + 1);
tmp = realloc(*haystack, strlen(*haystack) + 1);
if (!tmp) {
fprintf(stderr, "Out of memory!\n");
msg_gerr("Out of memory!\n");
exit(1);
}
*haystack = tmp;
@ -549,7 +549,7 @@ int check_erased_range(struct flashchip *flash, int start, int len)
uint8_t *cmpbuf = malloc(len);
if (!cmpbuf) {
fprintf(stderr, "Could not allocate memory!\n");
msg_gerr("Could not allocate memory!\n");
exit(1);
}
memset(cmpbuf, 0xff, len);
@ -577,16 +577,16 @@ int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, c
goto out_free;
if (!flash->read) {
fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n");
msg_cerr("ERROR: flashrom has no read function for this flash chip.\n");
return 1;
}
if (!readbuf) {
fprintf(stderr, "Could not allocate memory!\n");
msg_gerr("Could not allocate memory!\n");
exit(1);
}
if (start + len > flash->total_size * 1024) {
fprintf(stderr, "Error: %s called with start 0x%x + len 0x%x >"
msg_gerr("Error: %s called with start 0x%x + len 0x%x >"
" total_size 0x%x\n", __func__, start, len,
flash->total_size * 1024);
ret = -1;
@ -614,7 +614,7 @@ int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, c
if (cmpbuf[starthere - start + j] != readbuf[j]) {
/* Only print the first failure. */
if (!failcount++)
fprintf(stderr, "%s FAILED at 0x%08x! "
msg_cerr("%s FAILED at 0x%08x! "
"Expected=0x%02x, Read=0x%02x,",
message, starthere + j,
cmpbuf[starthere - start + j],
@ -623,7 +623,7 @@ int verify_range(struct flashchip *flash, uint8_t *cmpbuf, int start, int len, c
}
}
if (failcount) {
fprintf(stderr, " failed byte count from 0x%08x-0x%08x: 0x%x\n",
msg_cerr(" failed byte count from 0x%08x-0x%08x: 0x%x\n",
start, start + len - 1, failcount);
ret = -1;
}
@ -748,7 +748,7 @@ int generate_testpattern(uint8_t *buf, uint32_t size, int variant)
int i;
if (!buf) {
fprintf(stderr, "Invalid buffer!\n");
msg_gerr("Invalid buffer!\n");
return 1;
}
@ -836,7 +836,7 @@ int check_max_decode(enum chipbustype buses, uint32_t size)
if ((buses & CHIP_BUSTYPE_PARALLEL) &&
(max_rom_decode.parallel < size)) {
limitexceeded++;
printf_debug("Chip size %u kB is bigger than supported "
msg_pdbg("Chip size %u kB is bigger than supported "
"size %u kB of chipset/board/programmer "
"for %s interface, "
"probe/read/erase/write may fail. ", size / 1024,
@ -844,7 +844,7 @@ int check_max_decode(enum chipbustype buses, uint32_t size)
}
if ((buses & CHIP_BUSTYPE_LPC) && (max_rom_decode.lpc < size)) {
limitexceeded++;
printf_debug("Chip size %u kB is bigger than supported "
msg_pdbg("Chip size %u kB is bigger than supported "
"size %u kB of chipset/board/programmer "
"for %s interface, "
"probe/read/erase/write may fail. ", size / 1024,
@ -852,7 +852,7 @@ int check_max_decode(enum chipbustype buses, uint32_t size)
}
if ((buses & CHIP_BUSTYPE_FWH) && (max_rom_decode.fwh < size)) {
limitexceeded++;
printf_debug("Chip size %u kB is bigger than supported "
msg_pdbg("Chip size %u kB is bigger than supported "
"size %u kB of chipset/board/programmer "
"for %s interface, "
"probe/read/erase/write may fail. ", size / 1024,
@ -860,7 +860,7 @@ int check_max_decode(enum chipbustype buses, uint32_t size)
}
if ((buses & CHIP_BUSTYPE_SPI) && (max_rom_decode.spi < size)) {
limitexceeded++;
printf_debug("Chip size %u kB is bigger than supported "
msg_pdbg("Chip size %u kB is bigger than supported "
"size %u kB of chipset/board/programmer "
"for %s interface, "
"probe/read/erase/write may fail. ", size / 1024,
@ -873,7 +873,7 @@ int check_max_decode(enum chipbustype buses, uint32_t size)
*/
if (bitcount(buses) > limitexceeded)
/* FIXME: This message is designed towards CLI users. */
printf_debug("There is at least one common chip/programmer "
msg_pdbg("There is at least one common chip/programmer "
"interface which can support a chip of this size. "
"You can try --force at your own risk.\n");
return 1;
@ -934,7 +934,7 @@ notfound:
if (!flash || !flash->name)
return NULL;
printf("%s chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n",
msg_cinfo("%s chip \"%s %s\" (%d KB, %s) at physical address 0x%lx.\n",
force ? "Assuming" : "Found",
flash->vendor, flash->name, flash->total_size,
flashbuses_to_text(flash->bustype), base);
@ -950,12 +950,12 @@ int verify_flash(struct flashchip *flash, uint8_t *buf)
int ret;
int total_size = flash->total_size * 1024;
printf("Verifying flash... ");
msg_cinfo("Verifying flash... ");
ret = verify_range(flash, buf, 0, total_size, NULL);
if (!ret)
printf("VERIFIED. \n");
msg_cinfo("VERIFIED. \n");
return ret;
}
@ -968,17 +968,17 @@ int read_flash(struct flashchip *flash, char *filename)
unsigned char *buf = calloc(size, sizeof(char));
if (!filename) {
printf("Error: No filename specified.\n");
msg_gerr("Error: No filename specified.\n");
return 1;
}
if ((image = fopen(filename, "wb")) == NULL) {
perror(filename);
exit(1);
}
printf("Reading flash... ");
msg_cinfo("Reading flash... ");
if (!flash->read) {
printf("FAILED!\n");
fprintf(stderr, "ERROR: flashrom has no read function for this flash chip.\n");
msg_cinfo("FAILED!\n");
msg_cerr("ERROR: flashrom has no read function for this flash chip.\n");
return 1;
} else
flash->read(flash, buf, 0, size);
@ -986,7 +986,7 @@ int read_flash(struct flashchip *flash, char *filename)
numbytes = fwrite(buf, 1, size, image);
fclose(image);
free(buf);
printf("%s.\n", numbytes == size ? "done" : "FAILED");
msg_cinfo("%s.\n", numbytes == size ? "done" : "FAILED");
if (numbytes != size)
return 1;
return 0;
@ -1028,7 +1028,7 @@ int selfcheck_eraseblocks(struct flashchip *flash)
}
/* Empty eraseblock definition with erase function. */
if (!done && eraser.block_erase)
msg_pspew("Strange: Empty eraseblock definition with "
msg_gspew("Strange: Empty eraseblock definition with "
"non-empty erase function. Not an error.\n");
if (!done)
continue;
@ -1065,31 +1065,31 @@ int erase_flash(struct flashchip *flash)
int i, j, k, ret = 0, found = 0;
unsigned int start, len;
printf("Erasing flash chip... ");
msg_cinfo("Erasing flash chip... ");
for (k = 0; k < NUM_ERASEFUNCTIONS; k++) {
unsigned int done = 0;
struct block_eraser eraser = flash->block_erasers[k];
printf_debug("Looking at blockwise erase function %i... ", k);
msg_cdbg("Looking at blockwise erase function %i... ", k);
if (!eraser.block_erase && !eraser.eraseblocks[0].count) {
printf_debug("not defined. "
msg_cdbg("not defined. "
"Looking for another erase function.\n");
continue;
}
if (!eraser.block_erase && eraser.eraseblocks[0].count) {
printf_debug("eraseblock layout is known, but no "
msg_cdbg("eraseblock layout is known, but no "
"matching block erase function found. "
"Looking for another erase function.\n");
continue;
}
if (eraser.block_erase && !eraser.eraseblocks[0].count) {
printf_debug("block erase function found, but "
msg_cdbg("block erase function found, but "
"eraseblock layout is unknown. "
"Looking for another erase function.\n");
continue;
}
found = 1;
printf_debug("trying... ");
msg_cdbg("trying... ");
for (i = 0; i < NUM_ERASEREGIONS; i++) {
/* count==0 for all automatically initialized array
* members so the loop below won't be executed for them.
@ -1097,7 +1097,7 @@ int erase_flash(struct flashchip *flash)
for (j = 0; j < eraser.eraseblocks[i].count; j++) {
start = done + eraser.eraseblocks[i].size * j;
len = eraser.eraseblocks[i].size;
printf_debug("0x%06x-0x%06x, ", start,
msg_cdbg("0x%06x-0x%06x, ", start,
start + len - 1);
ret = eraser.block_erase(flash, start, len);
if (ret)
@ -1108,27 +1108,27 @@ int erase_flash(struct flashchip *flash)
done += eraser.eraseblocks[i].count *
eraser.eraseblocks[i].size;
}
printf_debug("\n");
msg_cdbg("\n");
/* If everything is OK, don't try another erase function. */
if (!ret)
break;
}
if (!found) {
fprintf(stderr, "ERROR: flashrom has no erase function for this flash chip.\n");
msg_cerr("ERROR: flashrom has no erase function for this flash chip.\n");
return 1;
}
if (ret) {
fprintf(stderr, "FAILED!\n");
msg_cerr("FAILED!\n");
} else {
printf("SUCCESS.\n");
msg_cinfo("SUCCESS.\n");
}
return ret;
}
void emergency_help_message(void)
{
fprintf(stderr, "Your flash chip is in an unknown state.\n"
msg_gerr("Your flash chip is in an unknown state.\n"
"Get help on IRC at irc.freenode.net (channel #flashrom) or\n"
"mail flashrom@flashrom.org!\n--------------------"
"-----------------------------------------------------------\n"
@ -1140,11 +1140,11 @@ void list_programmers(char *delim)
{
enum programmer p;
for (p = 0; p < PROGRAMMER_INVALID; p++) {
printf("%s", programmer_table[p].name);
msg_ginfo("%s", programmer_table[p].name);
if (p < PROGRAMMER_INVALID - 1)
printf("%s", delim);
msg_ginfo("%s", delim);
}
printf("\n");
msg_ginfo("\n");
}
void print_sysinfo(void)
@ -1183,7 +1183,7 @@ void print_sysinfo(void)
void print_version(void)
{
printf("flashrom v%s", flashrom_version);
msg_ginfo("flashrom v%s\n", flashrom_version);
print_sysinfo();
}
@ -1196,16 +1196,16 @@ int selfcheck(void)
* if more errors exist.
*/
if (ARRAY_SIZE(programmer_table) - 1 != PROGRAMMER_INVALID) {
fprintf(stderr, "Programmer table miscompilation!\n");
msg_gerr("Programmer table miscompilation!\n");
ret = 1;
}
if (spi_programmer_count - 1 != SPI_CONTROLLER_INVALID) {
fprintf(stderr, "SPI programmer table miscompilation!\n");
msg_gerr("SPI programmer table miscompilation!\n");
ret = 1;
}
#if BITBANG_SPI_SUPPORT == 1
if (bitbang_spi_master_count - 1 != BITBANG_SPI_INVALID) {
fprintf(stderr, "Bitbanging SPI master table miscompilation!\n");
msg_gerr("Bitbanging SPI master table miscompilation!\n");
ret = 1;
}
#endif
@ -1218,36 +1218,36 @@ int selfcheck(void)
void check_chip_supported(struct flashchip *flash)
{
if (TEST_OK_MASK != (flash->tested & TEST_OK_MASK)) {
printf("===\n");
msg_cinfo("===\n");
if (flash->tested & TEST_BAD_MASK) {
printf("This flash part has status NOT WORKING for operations:");
msg_cinfo("This flash part has status NOT WORKING for operations:");
if (flash->tested & TEST_BAD_PROBE)
printf(" PROBE");
msg_cinfo(" PROBE");
if (flash->tested & TEST_BAD_READ)
printf(" READ");
msg_cinfo(" READ");
if (flash->tested & TEST_BAD_ERASE)
printf(" ERASE");
msg_cinfo(" ERASE");
if (flash->tested & TEST_BAD_WRITE)
printf(" WRITE");
printf("\n");
msg_cinfo(" WRITE");
msg_cinfo("\n");
}
if ((!(flash->tested & TEST_BAD_PROBE) && !(flash->tested & TEST_OK_PROBE)) ||
(!(flash->tested & TEST_BAD_READ) && !(flash->tested & TEST_OK_READ)) ||
(!(flash->tested & TEST_BAD_ERASE) && !(flash->tested & TEST_OK_ERASE)) ||
(!(flash->tested & TEST_BAD_WRITE) && !(flash->tested & TEST_OK_WRITE))) {
printf("This flash part has status UNTESTED for operations:");
msg_cinfo("This flash part has status UNTESTED for operations:");
if (!(flash->tested & TEST_BAD_PROBE) && !(flash->tested & TEST_OK_PROBE))
printf(" PROBE");
msg_cinfo(" PROBE");
if (!(flash->tested & TEST_BAD_READ) && !(flash->tested & TEST_OK_READ))
printf(" READ");
msg_cinfo(" READ");
if (!(flash->tested & TEST_BAD_ERASE) && !(flash->tested & TEST_OK_ERASE))
printf(" ERASE");
msg_cinfo(" ERASE");
if (!(flash->tested & TEST_BAD_WRITE) && !(flash->tested & TEST_OK_WRITE))
printf(" WRITE");
printf("\n");
msg_cinfo(" WRITE");
msg_cinfo("\n");
}
/* FIXME: This message is designed towards CLI users. */
printf("Please email a report to flashrom@flashrom.org if any "
msg_cinfo("Please email a report to flashrom@flashrom.org if any "
"of the above operations\nwork correctly for you with "
"this flash part. Please include the flashrom\noutput "
"with the additional -V option for all operations you "
@ -1278,13 +1278,13 @@ int doit(struct flashchip *flash, int force, char *filename, int read_it, int wr
if (erase_it) {
if (flash->tested & TEST_BAD_ERASE) {
fprintf(stderr, "Erase is not working on this chip. ");
msg_cerr("Erase is not working on this chip. ");
if (!force) {
fprintf(stderr, "Aborting.\n");
msg_cerr("Aborting.\n");
programmer_shutdown();
return 1;
} else {
fprintf(stderr, "Continuing anyway.\n");
msg_cerr("Continuing anyway.\n");
}
}
if (flash->unlock)
@ -1310,24 +1310,24 @@ int doit(struct flashchip *flash, int force, char *filename, int read_it, int wr
flash->unlock(flash);
if (flash->tested & TEST_BAD_ERASE) {
fprintf(stderr, "Erase is not working on this chip "
msg_cerr("Erase is not working on this chip "
"and erase is needed for write. ");
if (!force) {
fprintf(stderr, "Aborting.\n");
msg_cerr("Aborting.\n");
programmer_shutdown();
return 1;
} else {
fprintf(stderr, "Continuing anyway.\n");
msg_cerr("Continuing anyway.\n");
}
}
if (flash->tested & TEST_BAD_WRITE) {
fprintf(stderr, "Write is not working on this chip. ");
msg_cerr("Write is not working on this chip. ");
if (!force) {
fprintf(stderr, "Aborting.\n");
msg_cerr("Aborting.\n");
programmer_shutdown();
return 1;
} else {
fprintf(stderr, "Continuing anyway.\n");
msg_cerr("Continuing anyway.\n");
}
}
if ((image = fopen(filename, "rb")) == NULL) {
@ -1341,7 +1341,7 @@ int doit(struct flashchip *flash, int force, char *filename, int read_it, int wr
exit(1);
}
if (image_stat.st_size != flash->total_size * 1024) {
fprintf(stderr, "Error: Image size doesn't match\n");
msg_gerr("Error: Image size doesn't match\n");
programmer_shutdown();
exit(1);
}
@ -1352,7 +1352,7 @@ int doit(struct flashchip *flash, int force, char *filename, int read_it, int wr
#endif
fclose(image);
if (numbytes != size) {
fprintf(stderr, "Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size);
msg_gerr("Error: Failed to read file. Got %ld bytes, wanted %ld!\n", numbytes, size);
programmer_shutdown();
return 1;
}
@ -1365,20 +1365,20 @@ int doit(struct flashchip *flash, int force, char *filename, int read_it, int wr
// ////////////////////////////////////////////////////////////
if (write_it) {
printf("Writing flash chip... ");
msg_cinfo("Writing flash chip... ");
if (!flash->write) {
fprintf(stderr, "Error: flashrom has no write function for this flash chip.\n");
msg_cerr("Error: flashrom has no write function for this flash chip.\n");
programmer_shutdown();
return 1;
}
ret = flash->write(flash, buf);
if (ret) {
fprintf(stderr, "FAILED!\n");
msg_cerr("FAILED!\n");
emergency_help_message();
programmer_shutdown();
return 1;
} else {
printf("COMPLETE.\n");
msg_cinfo("COMPLETE.\n");
}
}

2
hwaccess.c
View File

@ -41,7 +41,7 @@ void get_io_perms(void)
#else
if (iopl(3) != 0) {
#endif
fprintf(stderr, "ERROR: Could not get I/O privileges (%s).\n"
msg_perr("ERROR: Could not get I/O privileges (%s).\n"
"You need to be root.\n", strerror(errno));
exit(1);
}

79
ichspi.c
View File

@ -38,17 +38,6 @@
#include "chipdrivers.h"
#include "spi.h"
/* Change this to #define if you want lowlevel debugging of commands
* sent to the ICH/VIA SPI controller.
*/
#undef COMM_DEBUG
#ifdef COMM_DEBUG
#define msg_comm_debug printf_debug
#else
#define msg_comm_debug(...) do {} while (0)
#endif
/* ICH9 controller register definition */
#define ICH9_REG_FADDR 0x08 /* 32 Bits */
#define ICH9_REG_FDATA0 0x10 /* 64 Bytes */
@ -237,7 +226,7 @@ static int generate_opcodes(OPCODES * op)
uint32_t opmenu[2];
if (op == NULL) {
printf_debug("\n%s: null OPCODES pointer!\n", __func__);
msg_perr("\n%s: null OPCODES pointer!\n", __func__);
return -1;
}
@ -256,7 +245,7 @@ static int generate_opcodes(OPCODES * op)
opmenu[1] = REGREAD32(ICH9_REG_OPMENU + 4);
break;
default:
printf_debug("%s: unsupported chipset\n", __func__);
msg_perr("%s: unsupported chipset\n", __func__);
return -1;
}
@ -315,7 +304,7 @@ int program_opcodes(OPCODES * op)
opmenu[1] |= ((uint32_t) op->opcode[a].opcode) << ((a - 4) * 8);
}
printf_debug("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
msg_pdbg("\n%s: preop=%04x optype=%04x opmenu=%08x%08x\n", __func__, preop, optype, opmenu[0], opmenu[1]);
switch (spi_controller) {
case SPI_CONTROLLER_ICH7:
case SPI_CONTROLLER_VIA:
@ -331,7 +320,7 @@ int program_opcodes(OPCODES * op)
REGWRITE32(ICH9_REG_OPMENU + 4, opmenu[1]);
break;
default:
printf_debug("%s: unsupported chipset\n", __func__);
msg_perr("%s: unsupported chipset\n", __func__);
return -1;
}
@ -352,22 +341,22 @@ int ich_init_opcodes(void)
return 0;
if (ichspi_lock) {
printf_debug("Generating OPCODES... ");
msg_pdbg("Generating OPCODES... ");
curopcodes_done = &O_EXISTING;
rc = generate_opcodes(curopcodes_done);
} else {
printf_debug("Programming OPCODES... ");
msg_pdbg("Programming OPCODES... ");
curopcodes_done = &O_ST_M25P;
rc = program_opcodes(curopcodes_done);
}
if (rc) {
curopcodes = NULL;
printf_debug("failed\n");
msg_perr("failed\n");
return 1;
} else {
curopcodes = curopcodes_done;
printf_debug("done\n");
msg_pdbg("done\n");
return 0;
}
}
@ -439,7 +428,7 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
opmenu >>= 8;
}
if (opcode_index == 8) {
printf_debug("Opcode %x not found.\n", op.opcode);
msg_pdbg("Opcode %x not found.\n", op.opcode);
return 1;
}
temp16 |= ((uint16_t) (opcode_index & 0x07)) << 4;
@ -468,11 +457,12 @@ static int ich7_run_opcode(OPCODE op, uint32_t offset,
programmer_delay(10);
}
if (!timeout) {
printf_debug("timeout\n");
msg_perr("timeout\n");
}
/* FIXME: make sure we do not needlessly cause transaction errors. */
if ((REGREAD16(ICH7_REG_SPIS) & SPIS_FCERR) != 0) {
printf_debug("Transaction error!\n");
msg_pdbg("Transaction error!\n");
return 1;
}
@ -557,7 +547,7 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
opmenu >>= 8;
}
if (opcode_index == 8) {
printf_debug("Opcode %x not found.\n", op.opcode);
msg_pdbg("Opcode %x not found.\n", op.opcode);
return 1;
}
temp32 |= ((uint32_t) (opcode_index & 0x07)) << (8 + 4);
@ -586,11 +576,12 @@ static int ich9_run_opcode(OPCODE op, uint32_t offset,
programmer_delay(10);
}
if (!timeout) {
printf_debug("timeout\n");
msg_perr("timeout\n");
}
/* FIXME make sure we do not needlessly cause transaction errors. */
if ((REGREAD32(ICH9_REG_SSFS) & SSFS_FCERR) != 0) {
printf_debug("Transaction error!\n");
msg_pdbg("Transaction error!\n");
return 1;
}
@ -615,7 +606,7 @@ static int run_opcode(OPCODE op, uint32_t offset,
switch (spi_controller) {
case SPI_CONTROLLER_VIA:
if (datalength > 16) {
fprintf(stderr, "%s: Internal command size error for "
msg_perr("%s: Internal command size error for "
"opcode 0x%02x, got datalength=%i, want <=16\n",
__func__, op.opcode, datalength);
return SPI_INVALID_LENGTH;
@ -623,7 +614,7 @@ static int run_opcode(OPCODE op, uint32_t offset,
return ich7_run_opcode(op, offset, datalength, data, 16);
case SPI_CONTROLLER_ICH7:
if (datalength > 64) {
fprintf(stderr, "%s: Internal command size error for "
msg_perr("%s: Internal command size error for "
"opcode 0x%02x, got datalength=%i, want <=16\n",
__func__, op.opcode, datalength);
return SPI_INVALID_LENGTH;
@ -631,14 +622,14 @@ static int run_opcode(OPCODE op, uint32_t offset,
return ich7_run_opcode(op, offset, datalength, data, 64);
case SPI_CONTROLLER_ICH9:
if (datalength > 64) {
fprintf(stderr, "%s: Internal command size error for "
msg_perr("%s: Internal command size error for "
"opcode 0x%02x, got datalength=%i, want <=16\n",
__func__, op.opcode, datalength);
return SPI_INVALID_LENGTH;
}
return ich9_run_opcode(op, offset, datalength, data);
default:
printf_debug("%s: unsupported chipset\n", __func__);
msg_perr("%s: unsupported chipset\n", __func__);
}
/* If we ever get here, something really weird happened */
@ -652,14 +643,14 @@ static int ich_spi_write_page(struct flashchip *flash, uint8_t * bytes,
uint32_t remaining = page_size;
int towrite;
msg_comm_debug("ich_spi_write_page: offset=%d, number=%d, buf=%p\n",
msg_pspew("ich_spi_write_page: offset=%d, number=%d, buf=%p\n",
offset, page_size, bytes);
for (; remaining > 0; remaining -= towrite) {
towrite = min(remaining, maxdata);
if (spi_nbyte_program(offset + (page_size - remaining),
&bytes[page_size - remaining], towrite)) {
printf_debug("Error writing");
msg_perr("Error writing");
return 1;
}
}
@ -687,14 +678,14 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf)
spi_disable_blockprotect();
/* Erase first */
printf("Erasing flash before programming... ");
msg_pinfo("Erasing flash before programming... ");
if (erase_flash(flash)) {
fprintf(stderr, "ERASE FAILED!\n");
msg_perr("ERASE FAILED!\n");
return -1;
}
printf("done.\n");
msg_pinfo("done.\n");
printf("Programming page: \n");
msg_pinfo("Programming page: \n");
for (i = 0; i < total_size / erase_size; i++) {
if (spi_controller == SPI_CONTROLLER_VIA)
maxdata = 16;
@ -706,7 +697,7 @@ int ich_spi_write_256(struct flashchip *flash, uint8_t * buf)
}
}
printf("\n");
msg_pinfo("\n");
return rc;
}
@ -728,7 +719,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
/* FIXME: Reprogram opcodes if possible. Autodetect type of
* opcode by checking readcnt/writecnt.
*/
printf_debug("Invalid OPCODE 0x%02x\n", cmd);
msg_pdbg("Invalid OPCODE 0x%02x\n", cmd);
return SPI_INVALID_OPCODE;
}
@ -743,21 +734,21 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
*/
if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_WITH_ADDRESS) &&
(writecnt != 4)) {
fprintf(stderr, "%s: Internal command size error for opcode "
msg_perr("%s: Internal command size error for opcode "
"0x%02x, got writecnt=%i, want =4\n", __func__, cmd,
writecnt);
return SPI_INVALID_LENGTH;
}
if ((opcode->spi_type == SPI_OPCODE_TYPE_READ_NO_ADDRESS) &&
(writecnt != 1)) {
fprintf(stderr, "%s: Internal command size error for opcode "
msg_perr("%s: Internal command size error for opcode "
"0x%02x, got writecnt=%i, want =1\n", __func__, cmd,
writecnt);
return SPI_INVALID_LENGTH;
}
if ((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) &&
(writecnt < 4)) {
fprintf(stderr, "%s: Internal command size error for opcode "
msg_perr("%s: Internal command size error for opcode "
"0x%02x, got writecnt=%i, want >=4\n", __func__, cmd,
writecnt);
return SPI_INVALID_LENGTH;
@ -765,7 +756,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
if (((opcode->spi_type == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS) ||
(opcode->spi_type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS)) &&
(readcnt)) {
fprintf(stderr, "%s: Internal command size error for opcode "
msg_perr("%s: Internal command size error for opcode "
"0x%02x, got readcnt=%i, want =0\n", __func__, cmd,
readcnt);
return SPI_INVALID_LENGTH;
@ -792,7 +783,7 @@ int ich_spi_send_command(unsigned int writecnt, unsigned int readcnt,
result = run_opcode(*opcode, addr, count, data);
if (result) {
printf_debug("run OPCODE 0x%02x failed\n", opcode->opcode);
msg_pdbg("run OPCODE 0x%02x failed\n", opcode->opcode);
}
return result;
@ -817,7 +808,7 @@ int ich_spi_send_multicommand(struct spi_command *cmds)
*/
if (find_preop(curopcodes,
(cmds + 1)->writearr[0]) != -1) {
fprintf(stderr, "%s: Two subsequent "
msg_perr("%s: Two subsequent "
"preopcodes 0x%02x and 0x%02x, "
"ignoring the first.\n",
__func__, cmds->writearr[0],
@ -829,7 +820,7 @@ int ich_spi_send_multicommand(struct spi_command *cmds)
* No need to bother with fixups.
*/
if (!ichspi_lock) {
printf_debug("%s: FIXME: Add on-the-fly"
msg_pdbg("%s: FIXME: Add on-the-fly"
" reprogramming of the "
"chipset opcode list.\n",
__func__);

12
pcidev.c
View File

@ -45,7 +45,7 @@ uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar,
*/
addr = pci_read_long(dev, bar);
printf("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n",
msg_pinfo("Found \"%s %s\" (%04x:%04x, BDF %02x:%02x.%x).\n",
devs[i].vendor_name, devs[i].device_name,
dev->vendor_id, dev->device_id, dev->bus, dev->dev,
dev->func);
@ -66,7 +66,7 @@ uint32_t pcidev_validate(struct pci_dev *dev, uint32_t bar,
}
if (devs[i].status == NT) {
printf("===\nThis PCI device is UNTESTED. Please "
msg_pinfo("===\nThis PCI device is UNTESTED. Please "
"report the 'flashrom -p xxxx' output \n"
"to flashrom@flashrom.org if it works "
"for you. Thank you for your help!\n===\n");
@ -95,7 +95,7 @@ uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar,
filter.vendor = vendor_id;
if (pcidev_bdf != NULL) {
if ((msg = pci_filter_parse_slot(&filter, pcidev_bdf))) {
fprintf(stderr, "Error: %s\n", msg);
msg_perr("Error: %s\n", msg);
exit(1);
}
}
@ -112,10 +112,10 @@ uint32_t pcidev_init(uint16_t vendor_id, uint32_t bar,
/* Only continue if exactly one supported PCI dev has been found. */
if (found == 0) {
fprintf(stderr, "Error: No supported PCI device found.\n");
msg_perr("Error: No supported PCI device found.\n");
exit(1);
} else if (found > 1) {
fprintf(stderr, "Error: Multiple supported PCI devices found. "
msg_perr("Error: Multiple supported PCI devices found. "
"Use 'flashrom -p xxxx:bb:dd.f' \n"
"to explicitly select the card with the given BDF "
"(PCI bus, device, function).\n");
@ -130,7 +130,7 @@ void print_supported_pcidevs(struct pcidev_status *devs)
int i;
for (i = 0; devs[i].vendor_name != NULL; i++) {
printf("%s %s [%02x:%02x]%s\n", devs[i].vendor_name,
msg_pinfo("%s %s [%02x:%02x]%s\n", devs[i].vendor_name,
devs[i].device_name, devs[i].vendor_id,
devs[i].device_id,
(devs[i].status == NT) ? " (untested)" : "");

38
physmap.c
View File

@ -158,7 +158,7 @@ void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len)
if (-1 == fd_mem_cached) {
/* Open the memory device CACHED. */
if (-1 == (fd_mem_cached = open(MEM_DEV, O_RDWR))) {
perror("Critical error: open(" MEM_DEV ")");
msg_perr("Critical error: open(" MEM_DEV "): %s", strerror(errno));
exit(2);
}
}
@ -171,7 +171,7 @@ void *sys_physmap_ro_cached(unsigned long phys_addr, size_t len)
void physunmap(void *virt_addr, size_t len)
{
if (len == 0) {
printf_debug("Not unmapping zero size at %p\n", virt_addr);
msg_pspew("Not unmapping zero size at %p\n", virt_addr);
return;
}
@ -189,18 +189,18 @@ void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int
void *virt_addr;
if (len == 0) {
printf_debug("Not mapping %s, zero size at 0x%08lx.\n",
msg_pspew("Not mapping %s, zero size at 0x%08lx.\n",
descr, phys_addr);
return NULL;
}
if ((getpagesize() - 1) & len) {
fprintf(stderr, "Mapping %s at 0x%08lx, unaligned size 0x%lx.\n",
msg_perr("Mapping %s at 0x%08lx, unaligned size 0x%lx.\n",
descr, phys_addr, (unsigned long)len);
}
if ((getpagesize() - 1) & phys_addr) {
fprintf(stderr, "Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n",
msg_perr("Mapping %s, 0x%lx bytes at unaligned 0x%08lx.\n",
descr, (unsigned long)len, phys_addr);
}
@ -213,15 +213,17 @@ void *physmap_common(const char *descr, unsigned long phys_addr, size_t len, int
if (NULL == virt_addr) {
if (NULL == descr)
descr = "memory";
fprintf(stderr, "Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, (unsigned long)len, phys_addr);
msg_perr("Error accessing %s, 0x%lx bytes at 0x%08lx\n", descr, (unsigned long)len, phys_addr);
perror(MEM_DEV " mmap failed");
#ifdef __linux__
if (EINVAL == errno) {
fprintf(stderr, "In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n");
fprintf(stderr, "CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n");
fprintf(stderr, "Please check if either is enabled in your kernel before reporting a failure.\n");
fprintf(stderr, "You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n");
fprintf(stderr, "disabling the other option unfortunately requires a kernel recompile. Sorry!\n");
msg_perr("In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (<2.6.27),\n");
msg_perr("CONFIG_STRICT_DEVMEM (>=2.6.27) and CONFIG_X86_PAT kernel options.\n");
msg_perr("Please check if either is enabled in your kernel before reporting a failure.\n");
msg_perr("You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but\n");
msg_perr("disabling the other option unfortunately requires a kernel recompile. Sorry!\n");
}
#endif
if (!mayfail)
exit(3);
}
@ -306,7 +308,7 @@ int setup_cpu_msr(int cpu)
sprintf(msrfilename, "/dev/cpu/%d/msr", cpu);
if (fd_msr != -1) {
printf("MSR was already initialized\n");
msg_pinfo("MSR was already initialized\n");
return -1;
}
@ -314,7 +316,7 @@ int setup_cpu_msr(int cpu)
if (fd_msr < 0) {
perror("Error while opening /dev/cpu/0/msr");
printf("Did you run 'modprobe msr'?\n");
msg_pinfo("Did you run 'modprobe msr'?\n");
return -1;
}
@ -324,7 +326,7 @@ int setup_cpu_msr(int cpu)
void cleanup_cpu_msr(void)
{
if (fd_msr == -1) {
printf("No MSR initialized.\n");
msg_pinfo("No MSR initialized.\n");
return;
}
@ -389,7 +391,7 @@ int setup_cpu_msr(int cpu)
sprintf(msrfilename, "/dev/cpu%d", cpu);
if (fd_msr != -1) {
printf("MSR was already initialized\n");
msg_pinfo("MSR was already initialized\n");
return -1;
}
@ -397,7 +399,7 @@ int setup_cpu_msr(int cpu)
if (fd_msr < 0) {
perror("Error while opening /dev/cpu0");
printf("Did you install ports/sysutils/devcpu?\n");
msg_pinfo("Did you install ports/sysutils/devcpu?\n");
return -1;
}
@ -407,7 +409,7 @@ int setup_cpu_msr(int cpu)
void cleanup_cpu_msr(void)
{
if (fd_msr == -1) {
printf("No MSR initialized.\n");
msg_pinfo("No MSR initialized.\n");
return;
}
@ -445,7 +447,7 @@ int wrmsr(int addr, msr_t msr)
int setup_cpu_msr(int cpu)
{
printf("No MSR support for your OS yet.\n");
msg_pinfo("No MSR support for your OS yet.\n");
return -1;
}

8
spi.c
View File

@ -130,7 +130,7 @@ int spi_send_command(unsigned int writecnt, unsigned int readcnt,
const unsigned char *writearr, unsigned char *readarr)
{
if (!spi_programmer[spi_controller].command) {
fprintf(stderr, "%s called, but SPI is unsupported on this "
msg_perr("%s called, but SPI is unsupported on this "
"hardware. Please report a bug.\n", __func__);
return 1;
}
@ -142,7 +142,7 @@ int spi_send_command(unsigned int writecnt, unsigned int readcnt,
int spi_send_multicommand(struct spi_command *cmds)
{
if (!spi_programmer[spi_controller].multicommand) {
fprintf(stderr, "%s called, but SPI is unsupported on this "
msg_perr("%s called, but SPI is unsupported on this "
"hardware. Please report a bug.\n", __func__);
return 1;
}
@ -182,7 +182,7 @@ int default_spi_send_multicommand(struct spi_command *cmds)
int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
{
if (!spi_programmer[spi_controller].read) {
fprintf(stderr, "%s called, but SPI read is unsupported on this"
msg_perr("%s called, but SPI read is unsupported on this"
" hardware. Please report a bug.\n", __func__);
return 1;
}
@ -197,7 +197,7 @@ int spi_chip_read(struct flashchip *flash, uint8_t *buf, int start, int len)
int spi_chip_write_256(struct flashchip *flash, uint8_t *buf)
{
if (!spi_programmer[spi_controller].write_256) {
fprintf(stderr, "%s called, but SPI page write is unsupported "
msg_perr("%s called, but SPI page write is unsupported "
" on this hardware. Please report a bug.\n", __func__);
return 1;
}