From 32e5aca1a9ae395adee708a7a9c0668f9ee03755 Mon Sep 17 00:00:00 2001
From: Victor <vlim@gigadevice.com>
Date: Mon, 21 Oct 2024 21:33:44 +0000
Subject: [PATCH] flashchips: add GD25F128F

GD25F128F: 3V 128Mbit, high performance

Tested on ch347 with erase, write, read, and protection
Corrected the OTP statement.

Change-Id: I14c0905f50e92492287d50f8377790b997c4acfe
Signed-off-by: Victor <vlim@gigadevice.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/84827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
---
 flashchips.c         | 45 ++++++++++++++++++++++++++++++++++++++++++++
 include/flashchips.h |  1 +
 2 files changed, 46 insertions(+)

diff --git a/flashchips.c b/flashchips.c
index f48007809..c32159df3 100644
--- a/flashchips.c
+++ b/flashchips.c
@@ -8188,6 +8188,51 @@ const struct flashchip flashchips[] = {
 		.decode_range	= DECODE_RANGE_SPI25,
 	},
 
+{
+		.vendor		= "GigaDevice",
+		.name		= "GD25F128F",
+		.bustype	= BUS_SPI,
+		.manufacture_id	= GIGADEVICE_ID,
+		.model_id	= GIGADEVICE_GD25F128F,
+		.total_size	= 16384,
+		.page_size	= 256,
+		/* OTP: 3x2048B; read 0x48; write 0x42, erase 0x44 */
+		.feature_bits	= FEATURE_WRSR_WREN | FEATURE_OTP | FEATURE_WRSR2 | FEATURE_WRSR3,
+		.tested		= TEST_OK_PREWB,
+		.probe		= PROBE_SPI_RDID,
+		.probe_timing	= TIMING_ZERO,
+		.block_erasers	=
+		{
+			{
+				.eraseblocks = { {4 * 1024, 4096} },
+				.block_erase = SPI_BLOCK_ERASE_20,
+			}, {
+				.eraseblocks = { {32 * 1024, 512} },
+				.block_erase = SPI_BLOCK_ERASE_52,
+			}, {
+				.eraseblocks = { {64 * 1024, 256} },
+				.block_erase = SPI_BLOCK_ERASE_D8,
+			}, {
+				.eraseblocks = { {16 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_60,
+			}, {
+				.eraseblocks = { {16 * 1024 * 1024, 1} },
+				.block_erase = SPI_BLOCK_ERASE_C7,
+			}
+		},
+		.printlock	= SPI_PRETTYPRINT_STATUS_REGISTER_BP4_SRWD,
+		.unlock		= SPI_DISABLE_BLOCKPROTECT_BP4_SRWD, /* TODO: 2nd status reg (read with 0x35) */
+		.write		= SPI_CHIP_WRITE256,
+		.read		= SPI_CHIP_READ, /* Fast read (0x0B) and multi I/O supported */
+		.voltage	= {2700, 3600},
+		.reg_bits	=
+		{
+			.bp     = {{STATUS1, 2, RW}, {STATUS1, 3, RW}, {STATUS1, 4, RW}, {STATUS1, 5, RW}},
+			.tb     = {STATUS1, 6, RW},	/* Called BP4 in datasheet, acts like TB */
+		},
+		.decode_range	= DECODE_RANGE_SPI25,
+	},
+
 	{
 		.vendor		= "GigaDevice",
 		.name		= "GD25F256F",
diff --git a/include/flashchips.h b/include/flashchips.h
index 886ddc9ef..719486e95 100644
--- a/include/flashchips.h
+++ b/include/flashchips.h
@@ -402,6 +402,7 @@
 #define GIGADEVICE_GD25VQ80C	0x4214
 #define GIGADEVICE_GD25VQ16C	0x4215
 #define GIGADEVICE_GD25F64F	0x4317
+#define GIGADEVICE_GD25F128F	0x4318
 #define GIGADEVICE_GD25F256F	0x4319
 #define GIGADEVICE_GD25LQ40	0x6013
 #define GIGADEVICE_GD25LQ80	0x6014