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mirror of https://review.coreboot.org/flashrom.git synced 2025-08-17 20:30:16 +02:00

Add Gemini Lake support

The SPI hardware is pretty much unchanged from Apollo Lake. However, the
IFD differs significantly enough to require special handling.

Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: I8843ace1f024da04c80b419011841ccae4e48990
This commit is contained in:
Angel Pons
2020-07-10 17:04:10 +02:00
parent c117378478
commit 36c401dc3c
6 changed files with 37 additions and 7 deletions

View File

@@ -127,6 +127,7 @@ static void usage(char *argv[], const char *error)
"\t- \"ich10\",\n"
"\t- \"silvermont\" for chipsets from Intel's Silvermont architecture (e.g. Bay Trail),\n"
"\t- \"apollo\" for Intel's Apollo Lake SoC.\n"
"\t- \"gemini\" for Intel's Gemini Lake SoC.\n"
"\t- \"5\" or \"ibex\" for Intel's 5 series chipsets,\n"
"\t- \"6\" or \"cougar\" for Intel's 6 series chipsets,\n"
"\t- \"7\" or \"panther\" for Intel's 7 series chipsets.\n"
@@ -230,6 +231,8 @@ int main(int argc, char *argv[])
cs = CHIPSET_400_SERIES_COMET_POINT;
else if (strcmp(csn, "apollo") == 0)
cs = CHIPSET_APOLLO_LAKE;
else if (strcmp(csn, "gemini") == 0)
cs = CHIPSET_GEMINI_LAKE;
}
ret = read_ich_descriptors_from_dump(buf, len, &cs, &desc);