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mirror of https://review.coreboot.org/flashrom.git synced 2025-07-02 06:23:18 +02:00

chipset_enable: Add Apollo Lake

It works the same as 100 series PCHs and on. The SPI device is at
0:0d.2, though. Mark as BAD until `ichspi` is revised.

Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Nico Huber
2019-01-18 14:23:02 +01:00
committed by Nico Huber
parent 908adf4589
commit 3750986348
2 changed files with 21 additions and 4 deletions

View File

@ -626,6 +626,7 @@ enum ich_chipset {
CHIPSET_9_SERIES_WILDCAT_POINT_LP,
CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
CHIPSET_C620_SERIES_LEWISBURG,
CHIPSET_APOLLO_LAKE,
};
/* ichspi.c */