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chipset_enable: Add Apollo Lake

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It works the same as 100 series PCHs and on. The SPI device is at
0:0d.2, though. Mark as BAD until `ichspi` is revised.

Change-Id: I7b1ad402ba562b7b977be111f8cf61f1be50843a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/30994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Nico Huber 2019-01-18 14:23:02 +01:00 committed by Nico Huber
parent 908adf4589
commit 3750986348
2 changed files with 21 additions and 4 deletions
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24
chipset_enable.c
View File

@ -598,6 +598,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
break; break;
case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_APOLLO_LAKE:
reg_name = "BIOS_SPI_BC"; reg_name = "BIOS_SPI_BC";
gcs = pci_read_long(dev, 0xdc); gcs = pci_read_long(dev, 0xdc);
bild = (gcs >> 7) & 1; bild = (gcs >> 7) & 1;
@ -649,6 +650,9 @@ static enum chipbustype enable_flash_ich_report_gcs(
static const struct boot_straps boot_straps_pch8_lp[] = static const struct boot_straps boot_straps_pch8_lp[] =
{ { "SPI", BUS_SPI }, { { "SPI", BUS_SPI },
{ "LPC", BUS_LPC | BUS_FWH } }; { "LPC", BUS_LPC | BUS_FWH } };
static const struct boot_straps boot_straps_apl[] =
{ { "SPI", BUS_SPI },
{ "reserved" } };
static const struct boot_straps boot_straps_unknown[] = static const struct boot_straps boot_straps_unknown[] =
{ { "unknown" }, { { "unknown" },
{ "unknown" }, { "unknown" },
@ -690,6 +694,9 @@ static enum chipbustype enable_flash_ich_report_gcs(
case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_C620_SERIES_LEWISBURG:
boot_straps = boot_straps_pch8_lp; boot_straps = boot_straps_pch8_lp;
break; break;
case CHIPSET_APOLLO_LAKE:
boot_straps = boot_straps_apl;
break;
case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet case CHIPSET_8_SERIES_WELLSBURG: // FIXME: check datasheet
case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all case CHIPSET_CENTERTON: // FIXME: Datasheet does not mention GCS at all
boot_straps = boot_straps_unknown; boot_straps = boot_straps_unknown;
@ -712,6 +719,7 @@ static enum chipbustype enable_flash_ich_report_gcs(
break; break;
case CHIPSET_100_SERIES_SUNRISE_POINT: case CHIPSET_100_SERIES_SUNRISE_POINT:
case CHIPSET_C620_SERIES_LEWISBURG: case CHIPSET_C620_SERIES_LEWISBURG:
case CHIPSET_APOLLO_LAKE:
bbs = (gcs >> 6) & 0x1; bbs = (gcs >> 6) & 0x1;
break; break;
default: default:
@ -866,7 +874,9 @@ static int enable_flash_pch100_shutdown(void *const pci_acc)
return 0; return 0;
} }
static int enable_flash_pch100_or_c620(struct pci_dev *const dev, const char *const name, const enum ich_chipset pch_generation) static int enable_flash_pch100_or_c620(
struct pci_dev *const dev, const char *const name,
const int slot, const int func, const enum ich_chipset pch_generation)
{ {
int ret = ERROR_FATAL; int ret = ERROR_FATAL;
@ -887,7 +897,7 @@ static int enable_flash_pch100_or_c620(struct pci_dev *const dev, const char *co
pci_init(pci_acc); pci_init(pci_acc);
register_shutdown(enable_flash_pch100_shutdown, pci_acc); register_shutdown(enable_flash_pch100_shutdown, pci_acc);
struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, 0x1f, 5); struct pci_dev *const spi_dev = pci_get_dev(pci_acc, dev->domain, dev->bus, slot, func);
if (!spi_dev) { if (!spi_dev) {
msg_perr("Can't allocate PCI device.\n"); msg_perr("Can't allocate PCI device.\n");
return ret; return ret;
@ -929,12 +939,17 @@ _freepci_ret:
static int enable_flash_pch100(struct pci_dev *const dev, const char *const name) static int enable_flash_pch100(struct pci_dev *const dev, const char *const name)
{ {
return enable_flash_pch100_or_c620(dev, name, CHIPSET_100_SERIES_SUNRISE_POINT); return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_100_SERIES_SUNRISE_POINT);
} }
static int enable_flash_c620(struct pci_dev *const dev, const char *const name) static int enable_flash_c620(struct pci_dev *const dev, const char *const name)
{ {
return enable_flash_pch100_or_c620(dev, name, CHIPSET_C620_SERIES_LEWISBURG); return enable_flash_pch100_or_c620(dev, name, 0x1f, 5, CHIPSET_C620_SERIES_LEWISBURG);
}
static int enable_flash_apl(struct pci_dev *const dev, const char *const name)
{
return enable_flash_pch100_or_c620(dev, name, 0x0d, 2, CHIPSET_APOLLO_LAKE);
} }
/* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley. /* Silvermont architecture: Bay Trail(-T/-I), Avoton/Rangeley.
@ -2011,6 +2026,7 @@ const struct penable chipset_enables[] = {
{0x8086, 0xa2c8, B_S, NT, "Intel", "B250", enable_flash_pch100}, {0x8086, 0xa2c8, B_S, NT, "Intel", "B250", enable_flash_pch100},
{0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100}, {0x8086, 0xa2c9, B_S, NT, "Intel", "Z370", enable_flash_pch100},
{0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100}, {0x8086, 0xa2d2, B_S, NT, "Intel", "X299", enable_flash_pch100},
{0x8086, 0x5ae8, B_S, BAD, "Intel", "Apollo Lake", enable_flash_apl},
#endif #endif
{0}, {0},
}; };

1
programmer.h
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@ -626,6 +626,7 @@ enum ich_chipset {
CHIPSET_9_SERIES_WILDCAT_POINT_LP, CHIPSET_9_SERIES_WILDCAT_POINT_LP,
CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */ CHIPSET_100_SERIES_SUNRISE_POINT, /* also 6th/7th gen Core i/o (LP) variants */
CHIPSET_C620_SERIES_LEWISBURG, CHIPSET_C620_SERIES_LEWISBURG,
CHIPSET_APOLLO_LAKE,
}; };
/* ichspi.c */ /* ichspi.c */