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Add support for Intel Silvermont: Bay Trail, Rangeley and Avoton

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The core of this patch to support Bay Trail originally came from the
Chromiumos flashrom repo and was modified by Sage to support the
Rangeley/Avoton parts as well.
Because that was not complicated enough already Stefan Tauner refactored
and refined everything. Bay Trail seems to be the first Atom SoC able to
support hwseq. No SPI Programming Guide could be obtained so it is
handled similarly to Lynx Point which seems to be its nearest relative.

Corresponding to flashrom svn r1844.

Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Marc Jones <marcj303@gmail.com>
Tested-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
Tested-by: Thomas Reardon <thomas_reardon@hotmail.com>
Tested-by: Wen Wang <wen.wang@adiengineering.com>
Acked-by: Marc Jones <marcj303@gmail.com>
Acked-by: Stefan Tauner <stefan.tauner@alumni.tuwien.ac.at>
This commit is contained in:
Duncan Laurie
2014-08-20 15:39:32 +00:00
committed by Stefan Tauner
parent 2ba9f6ebe5
commit 4095ed797f
5 changed files with 196 additions and 64 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
ichspi.c
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@ -612,7 +612,8 @@ static void ich_set_bbar(uint32_t min_addr)
bbar_off = 0x50;
break;
case CHIPSET_ICH8:
msg_perr("BBAR offset is unknown on ICH8!\n");
case CHIPSET_BAYTRAIL:
msg_pdbg("BBAR offset is unknown!\n");
return;
case CHIPSET_ICH9:
default: /* Future version might behave the same */
@ -1739,9 +1740,12 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen)
msg_pdbg("VSCC: ");
prettyprint_ich_reg_vscc(tmp, MSG_DEBUG, true);
} else {
ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
msg_pdbg("0xA0: 0x%08x (BBAR)\n",
ichspi_bbar);
if (ich_generation != CHIPSET_BAYTRAIL && desc_valid) {
ichspi_bbar = mmio_readl(ich_spibar + ICH9_REG_BBAR);
msg_pdbg("0xA0: 0x%08x (BBAR)\n",
ichspi_bbar);
ich_set_bbar(0);
}
if (desc_valid) {
tmp = mmio_readl(ich_spibar + ICH9_REG_LVSCC);
@ -1757,10 +1761,8 @@ int ich_init_spi(struct pci_dev *dev, void *spibar, enum ich_chipset ich_gen)
tmp = mmio_readl(ich_spibar + ICH9_REG_FPB);
msg_pdbg("0xD0: 0x%08x (FPB)\n", tmp);
}
ich_set_bbar(0);
}
msg_pdbg("\n");
if (desc_valid) {
if (read_ich_descriptors_via_fdo(ich_spibar, &desc) == ICH_RET_OK)
prettyprint_ich_descriptors(ich_gen, &desc);