openwrt/flashrom
1
0
Fork 0
mirror of https://review.coreboot.org/flashrom.git synced 2025-04-29 07:53:44 +02:00
Code Issues Releases Wiki Activity

atahpt: Refactor singleton states into reentrant pattern

Browse Source 
Move global singleton states into a struct and store within
the par_master data field for the life-time of the driver.

This is one of the steps on the way to move par_master data
memory management behind the initialisation API, for more
context see other patches under the same topic "register_master_api".

Implements: https://ticket.coreboot.org/issues/391

BUG=b:185191942
TEST=builds

Change-Id: I82e4c82916dc835e9462b80750b06f9d78701edf
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/flashrom/+/64963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anastasia Klimchuk <aklm@chromium.org>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This commit is contained in:
Alexander Goncharov 2022-06-04 11:06:25 +03:00 committed by Anastasia Klimchuk
parent 40997e30ac
commit 41337be92b
1 changed files with 27 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
atahpt.c
View File

@ -28,7 +28,9 @@
#define PCI_VENDOR_ID_HPT 0x1103
static uint32_t io_base_addr = 0;
struct atahpt_data {
uint32_t io_base_addr;
};
static const struct dev_entry ata_hpt[] = {
{0x1103, 0x0004, NT, "Highpoint", "HPT366/368/370/370A/372/372N"},
@ -41,15 +43,25 @@ static const struct dev_entry ata_hpt[] = {
static void atahpt_chip_writeb(const struct flashctx *flash, uint8_t val,
chipaddr addr)
{
OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
OUTB(val, io_base_addr + BIOS_ROM_DATA);
struct atahpt_data *data = flash->mst->par.data;
OUTL((uint32_t)addr, data->io_base_addr + BIOS_ROM_ADDR);
OUTB(val, data->io_base_addr + BIOS_ROM_DATA);
}
static uint8_t atahpt_chip_readb(const struct flashctx *flash,
const chipaddr addr)
{
OUTL((uint32_t)addr, io_base_addr + BIOS_ROM_ADDR);
return INB(io_base_addr + BIOS_ROM_DATA);
struct atahpt_data *data = flash->mst->par.data;
OUTL((uint32_t)addr, data->io_base_addr + BIOS_ROM_ADDR);
return INB(data->io_base_addr + BIOS_ROM_DATA);
}
static int atahpt_shutdown(void *par_data)
{
free(par_data);
return 0;
}
static const struct par_master par_master_atahpt = {
@ -61,11 +73,13 @@ static const struct par_master par_master_atahpt = {
.chip_writew = fallback_chip_writew,
.chip_writel = fallback_chip_writel,
.chip_writen = fallback_chip_writen,
.shutdown = atahpt_shutdown,
};
static int atahpt_init(void)
{
struct pci_dev *dev = NULL;
uint32_t io_base_addr;
uint32_t reg32;
if (rget_io_perms())
@ -84,7 +98,14 @@ static int atahpt_init(void)
reg32 |= (1 << 24);
rpci_write_long(dev, REG_FLASH_ACCESS, reg32);
return register_par_master(&par_master_atahpt, BUS_PARALLEL, NULL);
struct atahpt_data *data = calloc(1, sizeof(*data));
if (!data) {
msg_perr("Unable to allocate space for PAR master data\n");
return 1;
}
data->io_base_addr = io_base_addr;
return register_par_master(&par_master_atahpt, BUS_PARALLEL, data);
}
const struct programmer_entry programmer_atahpt = {